Bidirectional electromigration failure von Lim, M.K., Chouliaras, V.A., Gan, C.L., Dwyer, V.M.

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Quantifying the benefit of thread and data parallelism for fast motion estimation in MPEG-2 von CHOULIARAS, V. A, AGHA, S, JACOBS, T. R, DWYER, V. M

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Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec von Nunez-Yanez, Y.L., Chouliaras, V.A., Alfonso, D., Rovati, F.S.

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Fully Systolic FFT Architecture for Giga-sample Applications von Babionitakis, K., Chouliaras, V. A., Manolopoulos, K., Nakos, K., Reisis, D., Vlassopoulos, N.

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Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures von Jacobs, T.R., Chouliaras, V.A., Mulvaney, D.J.

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An efficient multiple precision floating-point Multiply-Add Fused unit von Manolopoulos, K., D. Reisis, Chouliaras, V.A.

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High-performance arithmetic coding VLSI macro for the H264 video compression standard von Nunez, J.L., Chouliaras, V.A.

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A configurable statistical lossless compression core based on variable order Markov modeling and arithmetic coding von Nunez-Yanez, J.L., Chouliaras, V.A.

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A multi-standard video accelerator based on a vector architecture von Chouliaras, V.A., Nunez, J.L., Mulvaney, D.J., Rovati, F.S., Alfonso, D.

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VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads von Chouliaras, V.A., Stevens, D., Dwyer, V.M.

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Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor von Touloupis, Emmanuel, Flint, James A., Chouliaras, Vassilios A., Ward, David D.

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Hardware implementation of a novel genetic algorithm von Zhu, Z., Mulvaney, D.J., Chouliaras, V.A.

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High-performance arithmetic coding VLSI macro for the H.264 video compression standard von Nunez, J.L., Chouliaras, V.A.

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A Novel [Delta][Sigma] Control System Processor and Its VLSI Implementation von Wu, Xiaofeng, Chouliaras, V.A, Nunez-Yanez, J.L, Goodall, R.M

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A Novel aIL Control System Processor and Its VLSI Implementation von Wu, Xiaofeng, Chouliaras, V A, Nunez-Yanez, J L, Goodall, R M

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Quantifying the benefit of thread and data parallelism for fast motion estimation in MPEG-2 von Chouliaras, V A, Agha, S, Jacobs, T R, Dwyer, V M

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Development of custom vector accelerator for high-performance speech coding von CHOULIARAS, Va, NUNEZ, J. L, KOUTSOMYTI, K, PARR, S. R, MULVANEY, D. J, DATTA, S

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Modelling multiple faults in fault-tolerant processor architectures von Touloupis, E, Flint, J A, Chouliaras, V A, Ward, D D

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Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations von Dwyer, Vincent M., Agha, Shahrukh, Chouliaras, Vassilios A.

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On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures von Chouliaras, Vasilios A., Dwyer, Vincent M., Agha, Sharukh

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