Treffer 1 - 20 von 340 für Suche 'Choon Hi Lee', Suchdauer: 0,64s Treffer weiter einschränken
  1. 1
    A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

    A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration von Yoo, Changsik, Kyung, Kye-Hyun, Lim, Kyunam, Lee, Hi-Choon, Chai, Joon-Wan, Heo, Nak-Won, Lee, Dong-Jin, Kim, Chang-Hyun


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  2. 2
    A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity

    A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity von Kyung, Kye-Hyun, Lee, Hi-Choon, Song, Ki-Whan, Song, Ho-Sung, Jung, Keewook, Moon, Joon-Seo, Kim, Byoung-Sul, Cho, Sung-Burn, Kim, Changhyun, Cho, Soo-In


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  3. 3
    Laryngeal mask insertion during target-controlled infusion of propofol

    Laryngeal mask insertion during target-controlled infusion of propofol von Baik, Hee Jung, Kim, Jong Hak, Lee, Choon Hi

    Veröffentlicht in Journal of clinical anesthesia

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  4. 4
    A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology

    A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology von Kye Hyun Kyung, Chi Wook Kim, Jae Young Lee, Jeong Hoon Kook, Sung Min Seo, Du Yeul Kim, Jun Hyung Kim, Jung Sunwoo, Hi Choon Lee, Chul Soo Kim, Byung Hoon Jeong, Young Soo Sohn, Sang Pyo Hong, Jae Hyung Lee, Jei Hwan Yoo, Soo In Cho


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  5. 5
    Test circuit and method for use in semiconductor memory device

    Test circuit and method for use in semiconductor memory device von Lee, Hi-Choon

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  6. 6
    Parallel bit test circuits for testing semiconductor memory devices and related methods

    Parallel bit test circuits for testing semiconductor memory devices and related methods von Lee, Hi-Choon

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  7. 7
    Clock signal generation device and memory device including the same

    Clock signal generation device and memory device including the same von Seo Sung-Whan, Kalluru Vivek Venkata, Gangasani Venkataramana, Lee Hi-Choon

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  8. 8
    Semiconductor memory device with reduced multi-row address testing

    Semiconductor memory device with reduced multi-row address testing von Lee, Hi-choon

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  9. 9
    Semiconductor memory integrated circuit and layout method of the same

    Semiconductor memory integrated circuit and layout method of the same von Lee, Hi-Choon

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  10. 10
    High voltage generating circuit and semiconductor memory device having the same and method thereof

    High voltage generating circuit and semiconductor memory device having the same and method thereof von Kwon, Sang-hyuk, Lee, Hi-choon

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  11. 11
    Voltage boosting circuit and semiconductor device

    Voltage boosting circuit and semiconductor device von Nam, Jeong Sik, Lee, Hi Choon

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  12. 12
    High voltage generating circuit and semiconductor memory device having the same and method thereof

    High voltage generating circuit and semiconductor memory device having the same and method thereof von Kwon, Sang-hyuk, Lee, Hi-choon

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  13. 13
    Semiconductor memory device having high-speed input/output architecture

    Semiconductor memory device having high-speed input/output architecture von Lee, Hi-Choon

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  14. 14
    실험연구 : Histamine이 Lidocaine에 의한 신경 차단에 미치는 영향

    실험연구 : Histamine이 Lidocaine에 의한 신경 차단에 미치는 영향 von 조인해, In Hea Cho, 이춘희, Choon Hi Lee


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  15. 15
    Word line driver and semiconductor memory device having the same

    Word line driver and semiconductor memory device having the same von Son, Chris Ji Yoon, Lee, Hi-Choon

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  16. 16
    Semiconductor memory device having high-speed input/output architecture

    Semiconductor memory device having high-speed input/output architecture von Lee, Hi-Choon

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  17. 17
    Semiconductor memory device having improved replacement efficiency of defective word lines by redundancy word lines

    Semiconductor memory device having improved replacement efficiency of defective word lines by redundancy word lines von Lee, Hi-choon

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  18. 18
    Semiconductor memory device and method thereof

    Semiconductor memory device and method thereof von Byun, Young-yong, Lee, Hi-choon

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  19. 19
    Method of arranging fuses in a fuse box of a semiconductor memory device and a semiconductor memory device including such an arrangement

    Method of arranging fuses in a fuse box of a semiconductor memory device and a semiconductor memory device including such an arrangement von Choo, Chul-hwan, Lee, Hi-choon

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  20. 20
    Semiconductor memory device having improved replacement efficiency of defective word lines by redundancy word lines

    Semiconductor memory device having improved replacement efficiency of defective word lines by redundancy word lines von Lee, Hi-Choon

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