A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm von Wang, Chua-Chin, Chodisetti, L S S Pavan Kumar, Ke, Jhih-Ying, Lo, Cheng-Yao, Lee, Tzung-Je, Tolentino, Lean Karlo Santos

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A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD von Wang, Chua-Chin, Chodisetti, L S S Pavan Kumar, Liao, Bo-Hao, Vellanki, Pradyumna, Lee, Tzung-Je

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A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic von Wang, Chua-Chin, Chodisetti, L S S Pavan Kumar, Kamarajugadda, Durga Srikanth, Jose, Oliver Lexter July Alvarez, Vellanki, Pradyumna

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A single-chip PFM-controlled LED driver with 0.5% illuminance variation von Wang, Chua-Chin, Chodisetti, L S S Pavan Kumar, Lou, Pang-Yen, Hung, Chen-Cheng-Hung, Vellanki, Pradyumna, Sangalang, Ralph Gerard B., Tolentino, Lean Karlo S., Ronquillo, Tirso A.

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Equalization Based Soft Output Data Detection for Massive MU-MIMO-OFDM Using Coordinate Descent von Pavan Kumar Chodisetti, L. S. S., Donga, Madhusudan, Tella, Pavani Varma, Pasipalana Rao, K., Ramesh Chandra, K, Budumuru, Prudhvi Raj, Venkateswara Rao, Ch

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