A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs von Chickermane, V., Gallagher, P., Sage, J., Yuan, P., Chakravadhanula, K.

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Low cost at-speed testing using On-Product Clock Generation compatible with test compression von Keller, B, Chakravadhanula, K, Foutz, B, Chickermane, V, Malneedi, R, Snethen, T, Iyengar, V, Lackey, D, Grise, G

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DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks von Deutsch, S., Keller, B., Chickermane, V., Mukherjee, S., Sood, N., Goel, S. K., Chen, J., Mehta, A., Lee, F., Marinissen, E. J.

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Channel masking synthesis for efficient on-chip test compression von Chickermane, V., Foutz, B., Keller, B.

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SmartScan - Hierarchical test compression for pin-limited low power designs von Chakravadhanula, K., Chickermane, V., Pearl, D., Garg, A., Khurana, R., Mukherjee, S., Nagaraj, P.

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Addressing design for testability at the architectural level von Chickermane, V., Lee, J., Patel, J.H.

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Capture power reduction using clock gating aware test generation von Chakravadhanula, K., Chickermane, V., Keller, B., Gallagher, P., Narang, P.

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Automation of 3D-DfT Insertion von Deutsch, S., Chickermane, V., Keller, B., Mukherjee, S., Konijnenburg, M., Marinissen, E. J., Goel, S. K.

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An observability enhancement approach for improved testability and at-speed test von Rudnick, E.M., Chickermane, V., Patel, J.H.

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Automating IEEE 1500 Core Test-An EDA Perspective von Chakravadhanula, K., Chickermane, V.

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Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs? von Chakravadhanula, K., Chickermane, V., Keller, B., Gallagher, P., Uzzaman, A.

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Sequential circuit testability enhancement using a nonscan approach von Rudnick, E.M., Chickermane, V., Banerjee, P., Patel, J.H.

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Test Generation for State Retention Logic von Chakravadhanula, K., Chickermane, V., Keller, B., Gallagher, P., Gregor, S.

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A building block BIST methodology for SOC designs: a case study von Gallagher, P., Chickermane, V., Gregor, S., Pierre, T.S.

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An economic analysis and ROI model for nanometer test von Keller, B., Tegethoff, M., Bartenstein, T., Chickermane, V.

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A Scalable Architecture for On-Chip Compression: Options and Trade-Offs von Uzzaman, A., Keller, B., Chickermane, V.

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Low Power Reduced Pin Count Test Methodology von Chakravadhanula, K., Parimi, N., Foutz, B., Bing Li, Chickermane, V.

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Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology von Foutz, B., Chickermane, V., Bing Li, Linzer, H., Kunselman, G.

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System-on-chip testability using LSSD scan structures von Zarrineh, K., Upadhyaya, S.J., Chickermane, V.

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Practical Aspects of Delay Testing for Nanometer Chips von Chickermane, V., Keller, B., McCauley, K., Uzzaman, A.

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