Design and Reliability Assessment of Novel 3D-IC Packaging von Su, Y.-F., Chiang, K.-N., Liang, Steven Y.

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Characterization on acceleration-factor equation for packaging-solder joint reliability von Wu, K.-C., Chiang, K.-N.

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Thermal–mechanical behavior of the bonding wire for a power module subjected to the power cycling test von Hung, T.Y., Chiang, S.Y., Huang, C.J., Lee, C.C., Chiang, K.N.

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A Novel Acceleration-Factor Equation for Packaging-Solder Joint Reliability Assessment at Different Thermal Cyclic Loading Rates von Lee, C.-H., Wu, K.-C., Chiang, K.-N.

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Combining polynomial regression with unsupervised machine learning on wafer-level packaging reliability prediction von Liao, H H, Su, Qinghua, Chiang, K N

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AI-assisted reliability life prediction model for wafer-level packaging using the random forest method von Hsiao, H Y, Chiang, K N

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The Effect of Mechanical Stress on Electromigration Behavior von Chang, H.-H., Su, Y.-F., Liang, Steven Y., Chiang, K.-N.

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Study of shear locking effect on 3D solder joint reliability analysis von Huang, Y W, Chiang, K N

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Reliability Assessment of Wafer Level Package using Artificial Neural Network Regression Model von Chou, P. H., Chiang, K.N., Liang, Steven Y.

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Overview Study of Solder Joint Reliablity due to Creep Deformation von Ramachandran, V., Wu, K. C., Chiang, K. N.

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Development of a process modeling for residual stress assessment of multilayer thin film structure von Wang, H.J., Deng, H.A., Chiang, S.Y., Su, Y.F., Chiang, K.N.

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Investigation of the mechanical characteristics of the Cu/low-k BEOL under wire bonding process loading von Yuan, Cadmus C A, Chang, H M, Chiang, K N

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Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique von Wu, C.J., Hsieh, M.C., Chiu, C.C., Yew, M.C., Chiang, K.N.

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Material Shear Strength Assessment of AU/20SN Interconnection for High Temperature Applications von Liao, L. L., Chiang, K. N.

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Simulation of Wire Bonding Process Using Explicit Fem with Ale Remeshing Technology von Yang, C. C., Su, Y. F., Liang, Steven Y., Chiang, K. N.

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Developing an analytic methodology to accurately predict probing depth in integrated circuit structures von CHEN, K. M, CHIANG, K. N

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Analysis of Cu/Low- k structure under back end of line process von Chiu, C.C., Lee, C.C., Chou, T.L., Hsia, C.C., Chiang, K.N.

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Nonlinear and Temperature-Dependent Material Properties of AU/SN Alloy for Power Module von Liao, L. L., Chiang, K. N.

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The blood vasculature instructs lymphatic patterning in a SOX7‐dependent manner von Chiang, Ivy K N, Graus, Matthew S, Kirschnick, Nils, Davidson, Tara, Luu, Winnie, Harwood, Richard, Jiang, Keyi, Li, Bitong, Wong, Yew Yan, Moustaqil, Mehdi, Lesieur, Emmanuelle, Skoczylas, Renae, Kouskoff, Valerie, Kazenwadel, Jan, Arriola‐Martinez, Luis, Sierecki, Emma, Gambin, Yann, Alitalo, Kari, Kiefer, Friedmann, Harvey, Natasha L, Francois, Mathias

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Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via von Wu, C.J., Hsieh, M.C., Chiang, K.N.

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