ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC von Dai, Chia-Tsen, Ker, Ming-Dou

Volltext

Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process von Dai, Chia-Tsen, Ker, Ming-Dou

Volltext

Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications von Dai, Chia-Tsen, Ker, Ming-Dou

Volltext

Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- \mu \text 60-V/5-V BCD Technology von Dai, Chia-Tsen, Ker, Ming-Dou

Volltext

Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures von Chia-Tsen Dai, Ming-Dou Ker

Volltext

Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process von Yu-Ching Huang, Chia-Tsen Dai, Ming-Dou Ker

Volltext bestellen

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process von Chia-Tsen Dai, Po-Yen Chiu, Ming-Dou Ker, Fu-Yi Tsai, Yan-Hua Peng, Chia-Ku Tsai

Volltext