Single-Event Effect Characterization of 16 GHz Phase-Locked Loop in Sub-20 nm FinFET Technology von Sun, Hanhan, Wu, Zirui, Luo, Deng, Liang, Bin, Chen, Jianjun, Chi, Yaqing

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Soft Error Tolerant Bandgap Reference Utilizing Single-Event Transient Filtering Technique von Liu, Jingtian, Wang, Dongsheng, Liang, Bin, Chi, Yaqing, Luo, Deng, Xu, Shi

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Research on Single Event Transients in Linear Voltage Regulators in a 28 nm Bulk CMOS Technology von Shen, Fan, Chen, Jianjun, Chi, Yaqing, Liang, Bin, Sun, Hanhan, Wen, Yi, Guo, Hao, Wang, Xun

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ASET and TID Characterization of a Radiation Hardened Bandgap Voltage Reference in a 28-nm Bulk CMOS Technology von Chen, Jianjun, Chi, Yaqing, Liang, Bin, Yuan, Hengzhou, Wen, Yi, Xing, Haiyuan, Yao, Xiaohu

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Radiation Effects of Advanced Electronic Devices and Circuits von Chi, Yaqing, Cai, Chang, Cai, Li

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Effect of Cell Placement on Single-Event Transient Pulse in a Bulk FinFET Technology von Huang, Pengcheng, Zhao, Zhenyu, Chi, Yaqing, Liang, Bin, Ma, Chiyuan, Sun, Qian, Wu, Zhenyu

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Higher NMOS single event transient susceptibility compared to PMOS in sub-20nm bulk FinFET von Sun, Qian, Guo, Yang, Liang, Bin, Tao, Ming, Chi, Yaqing, Huang, Pengcheng, Wu, Zhenyu, Luo, Deng, Chen, Jianjun

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A Body-Biasing Technique for Single-Event Transient Mitigation in 28-nm Bulk CMOS Process von Liu, Jingtian, Liang, Bin, Guo, Yang, Chen, Jianjun, Chi, Yaqing, Sun, Qian, Song, Shengyu, Yuan, Hengzhou

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On-Chip Relative Single-Event Transient/Single- Event Upset Susceptibility Test Circuit for Integrated Circuits Working in Real Time von Hao, Peipei, Chen, Shuming, Wu, Zhenyu, Chi, Yaqing

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Radiation Effects of Advanced Electronic Devices and Circuits

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Design, Application, and Verification of the Novel SEU Tolerant Abacus-Type Layouts von Sun, Yi, Li, Zhi, He, Ze, Chi, Yaqing

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Gate breakdown induced stuck bits in sub-20 nm FinFET SRAM von Sun, Qian, Chi, Yaqing, Guo, Yang, Liang, Bin, Tao, Ming, Wu, Zhenyu, Guo, Hongxia, Zheng, Qiwen, Chen, Wangyong, Gao, Yulin, Zhao, Peixiong, Li, Xingji, Chen, Jianjun, Luo, Deng, Sun, Hanhan, Fang, Yahao

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Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits von Song, Ruiqiang, Shao, Jinjin, Chi, Yaqing, Liang, Bin, Chen, Jianjun, Wu, Zhenyu

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Heavy-Ion-Induced Charge Sharing Measurement With a Novel Uniform Vertical Inverter Chains (UniVIC) SEMT Test Structure von Huang, Pengcheng, Chen, Shuming, Chen, Jianjun, Liang, Bin, Chi, Yaqing

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A SET-Tolerant High-Frequency Multibiased Multiphase Voltage-Controlled Oscillator for Phase Interpolator-Based Clock and Data Recovery von Hengzhou, Yuan, Hao, Sang, Bin, Liang, Jianjun, Chen, Yaqing, Chi, Weixia, Xu, Yang, Guo

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SEU Tolerance Efficiency of Multiple Layout-Hardened 28 nm DICE D Flip-Flops von Chi, Yaqing, Cai, Chang, He, Ze, Wu, Zhenyu, Fang, Yahao, Chen, Jianjun, Liang, Bin

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Technology Dependency of TID Response for a Custom Bandgap Voltage Reference in 65 nm to 28 nm Bulk CMOS Technologies von Bin, Liang, Yi, Wen, Jianjun, Chen, Yaqing, Chi, Xiaohu, Yao

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TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials von Shao, Jinjin, Song, Ruiqiang, Chi, Yaqing, Liang, Bin, Wu, Zhenyu

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Experimental characterization of the dominant multiple nodes charge collection mechanism in metal oxide-semiconductor transistors von Song, Ruiqiang, Chen, Shuming, Chi, Yaqing, Wu, Zhenyu, Liang, Bin, Chen, Jianjun, Xu, Jingyan, Hao, Peipei, Yu, Junting

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Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies von Jianjun, Chen, Shuming, Chen, Yaqing, Chi, Bin, Liang

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