A 65 nm 2-Billion Transistor Quad-Core Itanium Processor von Stackhouse, B., Bhimji, S., Bostak, C., Bradley, D., Cherkauer, B., Desai, J., Francom, E., Gowan, M., Gronowski, P., Krueger, D., Morganti, C., Troyer, S.

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A 65-nm dual-core multithreaded Xeon® processor with 16-MB L3 cache von RUSU, Stefan, TAM, Simon, RAHUL DILIP LIMAYE, VORA, Sujal, MULJONO, Harry, AYERS, David, CHANG, Jonathan, CHERKAUER, Brian, STINSON, Jason, BENOIT, John, VARADA, Raj, LEUNG, Justin

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Itanium 2 processor 6M: higher frequency and larger L3 cache von Rusu, S., Muljono, H., Cherkauer, B.

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A 1.5-GHz 130-nm Itanium 2 processor with 6-MB on-die L3 cache von Rusu, S., Stinson, J., Tam, S., Leung, J., Muljono, H., Cherkauer, B.

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A unified design methodology for CMOS tapered buffers von Cherkauer, B.S., Friedman, E.G.

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Design of tapered buffers with local interconnect capacitance von Cherkauer, B.S., Friedman, E.G.

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A 65-nm Dual-Core Multithreaded Xeon registered Processor With 16-MB L3 Cache von Rusu, S, Tam, S, Muljono, H, Ayers, D, Chang, J, Cherkauer, B, Stinson, J, Benoit, J, Varada, R, Leung, J, Limaye, R D, Vora, S

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A 65-nm Dual-Core Multithreaded Xeon®Processor With 16-MB L3 Cache von Rusu, S., Tam, S., Muljono, H., Ayers, D., Chang, J., Cherkauer, B., Stinson, J., Benoit, J., Varada, R., Leung, J., Limaye, R.D., Vora, S.

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A 1.5-GHz 130-nm Itanium/sup /spl reg// 2 Processor with 6-MB on-die L3 cache von Rusu, S., Stinson, J., Tam, S., Leung, J., Muljono, H., Cherkauer, B.

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A 1.5-GHz 130-nm Itanium//reg// 2 Processor with 6-MB on-die L3 cache von Rusu, S, Stinson, J, Tam, S, Leung, J, Muljono, H, Cherkauer, B

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A 1.5-GHz 130-nm Itanium super( registered ) 2 Processor with 6-MB on-die L3 cache von Rusu, S, Stinson, J, Tam, S, Leung, J, Muljono, H, Cherkauer, B

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Channel width tapering of serially connected MOSFET's with emphasis on power dissipation von Cherkauer, B.S., Friedman, E.G.

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A hybrid radix-4/radix-8 low power signed multiplier architecture von CHERKAUER, B. S, FRIEDMAN, E. G

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A 65nm 95W Dual-Core Multi-Threaded Xeon® Processor with L3 Cache von Tam, S., Rusu, S., Chang, J., Vora, S., Cherkauer, B., Ayers, D.

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A hybrid radix-4/radix-8 low power, high speed multiplier architecture for wide bit widths von Cherkauer, B.S., Friedman, E.G.

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An Efficient Pipeline for Crop Image Extraction and Vegetation Index Derivation Using Unmanned Aerial Systems von Lyu, Beichen, Smith, Stuart D., Xue, Yexiang, Rainey, Katy M., Cherkauer, Keith

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A design methodology for low power, reduced area, reliable CMOS buffers von Cherkauer, B.S., Friedman, E.G.

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Unification of speed, power, area, and reliability in CMOS tapered buffer design von Cherkauer, B.S., Friedman, E.G.

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Design of tapered serial chains for reduced delay and power dissipation von Cherkauer, B.S., Friedman, E.G.

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Forming the Future of Agrohydrology von Smidt, S. J., Haacker, E. M. K., Bai, X., Cherkauer, K., Choat, B., Crompton, O., Deines, J. M., Groh, J., Guzmán, S. M., Hartman, S., Kendall, A. D., Safeeq, M., Kustas, W., McGill, B. M., Nocco, M. A., Pensky, J., Rapp, J., Schreiner‐Mcgraw, A., Sprenger, M., Wan, L., Weldegebriel, L., Zipper, S., Zoccatelli, D.

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