A 65 nm 2-Billion Transistor Quad-Core Itanium Processor von Stackhouse, B., Bhimji, S., Bostak, C., Bradley, D., Cherkauer, B., Desai, J., Francom, E., Gowan, M., Gronowski, P., Krueger, D., Morganti, C., Troyer, S.

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Itanium 2 processor 6M: higher frequency and larger L3 cache von Rusu, S., Muljono, H., Cherkauer, B.

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A 65-nm dual-core multithreaded Xeon® processor with 16-MB L3 cache von RUSU, Stefan, TAM, Simon, RAHUL DILIP LIMAYE, VORA, Sujal, MULJONO, Harry, AYERS, David, CHANG, Jonathan, CHERKAUER, Brian, STINSON, Jason, BENOIT, John, VARADA, Raj, LEUNG, Justin

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A 1.5-GHz 130-nm Itanium 2 processor with 6-MB on-die L3 cache von Rusu, S., Stinson, J., Tam, S., Leung, J., Muljono, H., Cherkauer, B.

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A unified design methodology for CMOS tapered buffers von Cherkauer, B.S., Friedman, E.G.

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Design of tapered buffers with local interconnect capacitance von Cherkauer, B.S., Friedman, E.G.

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An Efficient Pipeline for Crop Image Extraction and Vegetation Index Derivation Using Unmanned Aerial Systems von Lyu, Beichen, Smith, Stuart D., Xue, Yexiang, Rainey, Katy M., Cherkauer, Keith

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A 65-nm Dual-Core Multithreaded Xeon®Processor With 16-MB L3 Cache von Rusu, S., Tam, S., Muljono, H., Ayers, D., Chang, J., Cherkauer, B., Stinson, J., Benoit, J., Varada, R., Leung, J., Limaye, R.D., Vora, S.

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A 1.5-GHz 130-nm Itanium//reg// 2 Processor with 6-MB on-die L3 cache von Rusu, S, Stinson, J, Tam, S, Leung, J, Muljono, H, Cherkauer, B

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A 1.5-GHz 130-nm Itanium/sup /spl reg// 2 Processor with 6-MB on-die L3 cache von Rusu, S., Stinson, J., Tam, S., Leung, J., Muljono, H., Cherkauer, B.

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A hybrid radix-4/radix-8 low power signed multiplier architecture von CHERKAUER, B. S, FRIEDMAN, E. G

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A 1.5-GHz 130-nm Itanium super( registered ) 2 Processor with 6-MB on-die L3 cache von Rusu, S, Stinson, J, Tam, S, Leung, J, Muljono, H, Cherkauer, B

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Channel width tapering of serially connected MOSFET's with emphasis on power dissipation von Cherkauer, B.S., Friedman, E.G.

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Hydraulic Connection Between Lake Michigan and a Shallow Ground-Water Aquifer von Cherkauer, D. S., Zvibleman, B.

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A 65-nm Dual-Core Multithreaded Xeon registered Processor With 16-MB L3 Cache von Rusu, S, Tam, S, Muljono, H, Ayers, D, Chang, J, Cherkauer, B, Stinson, J, Benoit, J, Varada, R, Leung, J, Limaye, R D, Vora, S

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Influence of SST biases on future climate change projections von Ashfaq, Moetasim, Skinner, Chris B, Cherkauer, Keith

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Hull-Mounted Sea Surface Temperatures from Ships of Opportunity von Emery, W J, Cherkauer, K, Shannon, B, Reynolds, R W

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Groundwater flow into Lake Michigan from Wisconsin von Cherkauer, Douglas S., Hensel, Bruce R.

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A 65nm 95W Dual-Core Multi-Threaded Xeon® Processor with L3 Cache von Tam, S., Rusu, S., Chang, J., Vora, S., Cherkauer, B., Ayers, D.

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A hybrid radix-4/radix-8 low power, high speed multiplier architecture for wide bit widths von Cherkauer, B.S., Friedman, E.G.

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