Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions von Cheremisinov, D. I., Cheremisinova, L. D.

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Simulation of discrete control systems with parallelism of behavior von Cheremisinov, D. I., Cheremisinova, L. D.

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Canonization of graphs during transistor circuits decompilation von Cheremisinov, D. I., Cheremisinova, L. D.

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Logical gates recognition in a flat transistor circuit von Cheremisinov, D. I., Cheremisinova, L. D.

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Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit von Cheremisinov, D. I., Cheremisinova, L. D.

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A System for Logical Design of Custom CMOS VLSI Functional Blocks with Reduced Power Consumption von Bibilo, P. N., Avdeev, N. A., Kardash, S. N., Kirienko, N. A., Lankevich, Yu. Yu, Loginova, I. P., Romanov, V. I., Cheremisinov, D. I., Cheremisinova, L. D.

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PRALU language - the tool for verifying digital devices von D. I. Cheremisinov

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TECHNOLOGY MAPPING TOOL FOR VLSI CAD von D. I. Cheremisinov

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Protecting intellectual property in FPGA Xilinx design von Cheremisinov, D. I.

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POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS von D. I. Cheremisinov, L. D. Cheremisinova

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Synthesis of computer programs that implement finite automata von Cheremisinov, D. I.

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Programming of agents in the PRALU language von Cheremisinov, D. I., Cheremisinova, L. D.

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Custom Logic: A Toolkit for the Design of VLSI Custom Control MOS Logic von Bibilo, P. N., Vasil'kova, I. V., Kardash, S. N., Kirienko, N. A., Loginova, I. P., Novikov, Ya. A., Romanov, V. I., Toropov, N. R., Cheremisinov, D. I., Cheremisinova, L. D.

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The generation of graphs representing structural formulas of molecular isomers von Cheremisinov, D. I.

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Validation of the high-order polynomial models used in behavioral-level simulation von Loyka, S.L., Cheremisinov, I.D.

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Mechanical Stresses and Magnetic Properties of NiFe and CoNiFe Films Obtained by Electrochemical Deposition von Tikhonov, R. D., Polomoshnov, S. A., Amelichev, V. V., Cheremisinov, A. A., Potapov, V. S., Gorelov, D. V., Kasakov, Ju. V.

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Subcircuit Pattern Recognition in Transistor Level Circuits von Cheremisinov, D., Cheremisinova, L.

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Congruent Electrochemical Deposition of Co–Ni–Fe Films von Tikhonov, R. D., Cheremisinov, A. A., Tikhonov, M. R.

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Model Based Testing of Concurrent Systems Based on Reachability Graph Reduction von Cheremisinov, D., Cheremisinova, L.

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Ion Discharge in Electrochemical Deposition of CoNiFe Films von Tikhonov, R. D., Cheremisinov, A. A., Tikhonov, M. R.

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