Subcircuit Pattern Recognition in Transistor Level Circuits von Cheremisinov, D., Cheremisinova, L.

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Model Based Testing of Concurrent Systems Based on Reachability Graph Reduction von Cheremisinov, D., Cheremisinova, L.

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Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions von Cheremisinov, D. I., Cheremisinova, L. D.

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Simulation of discrete control systems with parallelism of behavior von Cheremisinov, D. I., Cheremisinova, L. D.

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Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit von Cheremisinov, D. I., Cheremisinova, L. D.

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Canonization of graphs during transistor circuits decompilation von Cheremisinov, D. I., Cheremisinova, L. D.

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Theoretical justification of the main parameters of the coulter group of the sod seeder for strip sowing von Sysuev, V. A., Demshin, S. L., Cheremisinov, D. A., Doronin, M. S.

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Logical gates recognition in a flat transistor circuit von Cheremisinov, D. I., Cheremisinova, L. D.

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Results of the research of the basic model of multifunctional tillage unit von Demshin, S. L., Cheremisinov, D. A., Ostal’tsev, V. P., Ilyichev, V. V.

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Justification of constructive technological scheme of multifunctional unit von Andreev, V L, Vasilyev, S A, Demshin, S L, Ilichev, V V, Cheremisinov, D A

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Universal implement for the basic soil cultivation with replaceable working bodies for tractors of a thrust class 3,0 von Dyomshin, S.L., Cheremisinov, D.A., Ostal'tsev, V.P.

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A System for Logical Design of Custom CMOS VLSI Functional Blocks with Reduced Power Consumption von Bibilo, P. N., Avdeev, N. A., Kardash, S. N., Kirienko, N. A., Lankevich, Yu. Yu, Loginova, I. P., Romanov, V. I., Cheremisinov, D. I., Cheremisinova, L. D.

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Determination of parameters of the opener group in the development of unit for pre-sowing soil cultivation and sowing von Cheremisinov, D A, Dyomshin, S L

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Perfecting of a construction of the unit for pre-sowing soil cultivation and sowing APPN-2,1 von Dyomshin, S L, Cheremisinov, D A, Vladimirov, E A

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Protecting intellectual property in FPGA Xilinx design von Cheremisinov, D. I.

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PRALU language - the tool for verifying digital devices von D. I. Cheremisinov

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TECHNOLOGY MAPPING TOOL FOR VLSI CAD von D. I. Cheremisinov

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POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS von D. I. Cheremisinov, L. D. Cheremisinova

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Synthesis of computer programs that implement finite automata von Cheremisinov, D. I.

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Improvement quality of strip sowing of grasses’ seeds into a sod von V. A. Sysuev, S. L. Dyomshin, D. A. Cheremisinov, M. S. Doronin

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