An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches von Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.

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Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs) von Yoonmyung Lee, Daeyeon Kim, Jin Cai, Lauer, Isaac, Chang, Leland, Koester, Steven J., Blaauw, David, Sylvester, Dennis

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Extremely scaled silicon nano-CMOS devices von Chang, L., Yang-kyu Choi, Ha, D., Ranade, P., Shiying Xiong, Bokor, J., Chenming Hu, King, T.J.

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CMOS circuit performance enhancement by surface orientation optimization von Chang, L., Leong, M., Yang, M.

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Sub-50 nm P-channel FinFET von Xuejue Huang, Wen-Chin Lee, Kuo, C., Hisamoto, D., Leland Chang, Kedzierski, J., Anderson, E., Takeuchi, H., Yang-Kyu Choi, Asano, K., Subramanian, V., Tsu-Jae King, Bokor, J., Chenming Hu

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Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs von Leland Chang, Yang, K.J., Yee-Chia Yeo, Polishchuk, I., Tsu-Jae King, Chenming Hu

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Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems von Rajendran, B., Yong Liu, Jae-sun Seo, Gopalakrishnan, K., Chang, Leland, Friedman, D. J., Ritter, M. B.

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Efficient AI System Design With Cross-Layer Approximate Computing von Venkataramani, Swagath, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Choi, Jungwook, Kang, Mingu, Agarwal, Ankur, Oh, Jinwook, Jain, Shubham, Babinsky, Tina, Cao, Nianzheng, Fox, Thomas, Fleischer, Bruce, Gristede, George, Guillorn, Michael, Haynie, Howard, Inoue, Hiroshi, Ishizaki, Kazuaki, Klaiber, Michael, Lo, Shih-Hsien, Maier, Gary, Mueller, Silvia, Scheuermann, Michael, Ogawa, Eri, Schaal, Marcel, Serrano, Mauricio, Silberman, Joel, Vezyrtzis, Christos, Wang, Wei, Yee, Fanchieh, Zhang, Jintao, Ziegler, Matthew, Zhou, Ching, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Srinivasan, Vijayalakshmi, Chang, Leland, Gopalakrishnan, Kailash

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A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation von Ditlow, G S, Montoye, R K, Storino, S N, Dance, S M, Ehrenreich, S, Fleischer, B M, Fox, T W, Holmes, K M, Mihara, J, Nakamura, Y, Onishi, S, Shearer, R, Wendel, D, Leland Chang

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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling von Lee, Sae Kyu, Agrawal, Ankur, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia M., Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Kar, Monodeep, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael R., Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

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Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation von Ji, B.L., Pearson, D.J., Lauer, I., Stellari, F., Frank, D.J., Chang, L., Ketchen, M.B.

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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC von Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey K., Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Rower, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

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Practical Strategies for Power-Efficient Computing Technologies von Chang, Leland, Frank, David J., Montoye, Robert K., Koester, Steven J., Ji, Brian L., Coteus, Paul W., Dennard, Robert H., Haensch, Wilfried

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A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering von Suyoung Bang, Jae-sun Seo, Chang, Leland, Blaauw, David, Sylvester, Dennis

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DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator von Venkataramani, Swagath, Choi, Jungwook, Srinivasan, Vijayalakshmi, Wang, Wei, Zhang, Jintao, Schaal, Marcel, Serrano, Mauricio J., Ishizaki, Kazuaki, Inoue, Hiroshi, Ogawa, Eri, Ohara, Moriyoshi, Chang, Leland, Gopalakrishnan, Kailash

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FinFET scaling to 10 nm gate length von Bin Yu, Leland Chang, Ahmed, S., Haihong Wang, Bell, S., Chih-Yuh Yang, Tabery, C., Chau Ho, Qi Xiang, Tsu-Jae King, Bokor, J., Chenming Hu, Ming-Ren Lin, Kyser, D.

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A 512kb 8T SRAM Macro Operating Down to 0.57V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45nm SOI CMOS von Qazi, Masood, Stawiasz, Kevin, Chang, Leland, Chandrakasan, Anantha P

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A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS von Qazi, Masood, Stawiasz, Kevin, Chang, Leland, Chandrakasan, Anantha P

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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons von Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., Friedman, D. J.

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Near-threshold operation for power-efficient computing?: it depends von Chang, Leland, Haensch, Wilfried

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