The importance of prepass code scheduling for superscalar and superpipelined processors von Chang, P.P., Lavery, D.M., Mahlke, S.A., Chen, W.Y., Hwu, W.-M.W.

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Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution von CHANG, P.-Y, HAO, E, PATT, Y. N, CHANG, P. P

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The superblock: An effective technique for VLIW and superscalar compilation von Hwu, Wen -Mei W., Mahlke, Scott A., Chen, William Y., Chang, Pohua P., Warter, Nancy J., Bringmann, Roger A., Ouellette, Roland G., Hank, Richard E., Kiyohara, Tokuzo, Haab, Grant E., Holm, John G., Lavery, Daniel M.

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IMPACT: an architectural framework for multiple-instruction-issue processors von Chang, P.P., Mahike, S.A., Chen, W.Y., Warier, N.J., Hwu, W.W.

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Three architectural models for compiler-controlled speculative execution von Chang, P.P., Warter, N.F., Mahlke, S.A., Chen, W.Y., Hwu, W.W.

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Achieving High Instruction Cache Performance With An Optimizing Compiler von Hisu, W.W., Pohua P. Chang

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Efficient instruction sequencing with inline target insertion von Hwu, W.W., Chang, P.P.

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Comparing Software And Hardware Schemes For Reducing The Cost Of Branches von Wen-mei W. Hwu, Conte, T.M., Pohua P. Chang

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Achieving high instruction cache performance with an optimizing compiler von Hwu, W W, Chang, P P

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Trace Selection For Compiling Large C Application Programs To Microcode von Pohua P. Chang, Wen-mei W. Hwu

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Efficient Instruction Sequencing with Inline Target Insertion von Hwu, Wen-mei W, Chang, Pohua P

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IMPACT: an architectural framework for multiple-instruction-issue processors von Chang, Pohua P., Mahlke, Scott A., Chen, William Y., Warter, Nancy J., Hwu, Wen-mei W.

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Exploiting parallel microprocessor microarchitectures with a compiler code generator von Hwu, W. W., Chang, P. P.

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Comparing software and hardware schemes for reducing the cost of branches von Hwu, W W, Conte, T M, Chang, P P

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The effect of code expanding optimizations on instruction cache design von Chen, William Y., Chang, Pohua P., Conte, Thomas M., Hwu, Wen-Mei W.

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Compiler code transformations for superscalar-based high-performance systems von Mahlke, S.A., Chen, W.Y., Gyllenhaal, J.C., Hwu, W.W., Chang, P.P., Kiyohara, T.

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IMPACT: an architectural framework for multiple-instruction-issue processors von Chang, Pohua P., Mahlke, Scott A., Chen, William Y., Warter, Nancy J., Hwu, Wen-mei W.

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Memory optimizations in the Intel Reference Compiler von Sridharan, K., Chang, Pohua, Banerjee, Utpal, Narayanaswamy, Ravi, Rao, Suresh

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The effect of code expanding optimizations on instruction cache design von Chen, W.Y., Chang, P.P., Conte, T.M., Hwu, W.W.

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Bidirectional scheduling: A new global code scheduling approach von Chang, Pohua, Chen, Dong-yuan, Lee, Yong-fong, Wu, Youfeng, Banerjee, Utpal

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