Resolution Effects in Chaotic Velocity Field Reconstruction from Passive Scalar Data von Chamberlain, Jeffrey D, McDonough, J. M

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Cache line demote infrastructure for multi-processor pipelines von Maslekar, Omkar, Chamberlain, Jeffrey D, Autee, Priya, Verplanke, Edwin, Herdrich, Andrew J, Shah, Rahul R

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LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY von LIU, Yen-Cheng, EAPATI, Soumya S, MATHEW ABRAHAM, Vinit, CHAMBERLAIN, Jeffrey D, NALLUSAMY, Eswaramoorthi

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Link affinitization to reduce transfer latency von Mathew Abraham, Vinit, Nallusamy, Eswaramoorthi, Chamberlain, Jeffrey D, Eachempati, Soumya S, Liu, Yen-Cheng

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LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY von LIU, Yen-Cheng, EAPATI, Soumya S, MATHEW ABRAHAM, Vinit, CHAMBERLAIN, Jeffrey D, NALLUSAMY, Eswaramoorthi

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CACHE LINE DEMOTE INFRASTRUCTURE FOR MULTI-PROCESSOR PIPELINES von SHAH, Rahul R, CHAMBERLAIN, Jeffrey D, AUTEE, Priya, MASLEKAR, Omkar, HERDRICH, Andrew J, VERPLANKE, Edwin

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LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY von LIU, Yen-Cheng, EAPATI, Soumya S, MATHEW ABRAHAM, Vinit, CHAMBERLAIN, Jeffrey D, NALLUSAMY, Eswaramoorthi

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Optimized caching agent with integrated directory cache von Chamberlain, Jeffrey D, Fahim, Bahaa, Strom, Samuel D, Jagannathan, Ashok

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CACHE LINE DEMOTE INFRASTRUCTURE FOR MULTI-PROCESSOR PIPELINES von SHAH, Rahul R, CHAMBERLAIN, Jeffrey D, AUTEE, Priya, MASLEKAR, Omkar, HERDRICH, Andrew J, VERPLANKE, Edwin

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Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement von Toll, Bret, HERDRICH, Andrew, MANDELBLAT, Julius, CHAMBERLAIN, Jeffrey D, IYER, Ravishankar, GIANOS, Christopher, SINGH, Ronak, VERPLANKE, Edwin

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LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY von LIU, Yen-Cheng, EAPATI, Soumya S, MATHEW ABRAHAM, Vinit, CHAMBERLAIN, Jeffrey D, NALLUSAMY, Eswaramoorthi

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Resolution effects in chaotic velocity field reconstruction from passive scalar data von Chamberlain, Jeffrey D., McDonough, J. M.

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MULTIPLE DIES HARDWARE PROCESSORS AND METHODS von VARMA, ANKUSH, CHAMBERLAIN, JEFFREY D, NIMMAGADDA, SRIKANTH, KUMASHIKAR, MAHESH K, CHRYSOS, GEORGE Z, GEETHA, VEDARAMAN, AYERS, JOHN R, MOLNAR, CARLETON L, SUBBAREDDY, DHEERAJ R, SISTLA, KRISHNAKANTH V, LIU, YENNG, SINGH, TEJPAL, PASDAST, GERALD, HALLECK, WILLIAM R, NASSIF, NEVINE, EAPATI, SIVA SOUMYA

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OPTIMIZED CACHING AGENT WITH INTEGRATED DIRECTORY CACHE von Chamberlain, Jeffrey D, Fahim, Bahaa, Strom, Samuel D, Jagannathan, Ashok

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SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS von LIU, Yen-Cheng, FAHIM, Bahaa, HALLNOR, Erik G, CHAMBERLAIN, Jeffrey D, VAN DOREN, Stephen R, JUAN, Antonio

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Multiple dies hardware processors and methods von Singh, Tejpal, Chamberlain, Jeffrey D, Sistla, Krishnakanth V, Kumashikar, Mahesh K, Geetha, Vedaraman, Ayers, John R, Pasdast, Gerald, Nassif, Nevine, Eachempati, Siva Soumya, Nimmagadda, Srikanth, Halleck, William R, Subbareddy, Dheeraj R, Liu, Yen-Cheng, Varma, Ankush, Chrysos, George Z, Molnar, Carleton L

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Function as a service (FaaS) system enhancements von Kumar, Mohan J, Doshi, Kshitij, Dahlen, Eric J, Rao, Anil, Babokin, Dmitry Yurievich, Bachmutsky, Alexander, Sane, Harshad, Haghighat, Mohammad R, Huang, Wenyong, Lemay, Michael, Firoozshahian, Amin, Bhuyan, Krishna, Zhang, Mingwei, Chamberlain, Jeffrey D, Melik-Adamyan, Areg, Iyer, Ravishankar R, Baghsorkhi, Sara, Tsai, Jr-Shian, Herdrich, Andrew J, Mohan, Anup, Peled, Leeor, Sun, Mingqiu, Sahita, Ravi, Steiner, Ian M, Durham, David M, Goh, Teck Joo, Prinke, Michael, Jain, Nilesh K, Raghuram, Yeluri, Sukhomlinov, Vadim A, Patel, Baiju V

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A METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTION HANDLING IN A PROCESSOR von LIU, Yen-Cheng, HUANG, Min, FAHIM, Bahaa, CHAMBERLAIN, Jeffrey D, GEETHA, Vedaraman

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Scalably mechanism to implement an instruction that monitors for writes to an address von Van Doren, Stephen R, Chamberlain, Jeffrey D, Fahim, Bahaa, Hallnor, Erik G, Juan, Antonio, Liu, Yen-Cheng

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VIRTUAL RETRY QUEUE von LIU, Yen-Cheng, FAHIM, Bahaa, CHAMBERLAIN, Jeffrey D

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