Engineering strained silicon on insulator wafers with the Smart CutTM technology von Ghyselen, B., Hartmann, J.-M., Ernst, T., Aulnette, C., Osternaud, B., Bogumilowicz, Y., Abbadie, A., Besson, P., Rayssac, O., Tiberj, A., Daval, N., Cayrefourq, I., Fournel, F., Moriceau, H., Di Nardo, C., Andrieu, F., Paillard, V., Cabié, M., Vincent, L., Snoeck, E., Cristiano, F., Rocher, A., Ponchet, A., Claverie, A., Boucaud, P., Semeria, M.-N., Bensahel, D., Kernevez, N., Mazure, C.

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Engineering strained silicon on insulator wafers with the Smart Cut TM technology von Ghyselen, B., Hartmann, J.-M., Ernst, T., Aulnette, C., Osternaud, B., Bogumilowicz, Y., Abbadie, A., Besson, P., Rayssac, O., Tiberj, A., Daval, N., Cayrefourq, I., Fournel, F., Moriceau, H., Di Nardo, C., Andrieu, F., Paillard, V., Cabié, M., Vincent, L., Snoeck, E., Cristiano, F., Rocher, A., Ponchet, A., Claverie, A., Boucaud, P., Semeria, M.-N., Bensahel, D., Kernevez, N., Mazure, C.

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Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL von Collaert, N., Rooyackers, R., Dilliway, G., Iyengar, V., Augendre, E., Leys, F., Cayrefourq, I., Ghyselen, B., Loo, R., Jurczak, M., Biesemans, S.

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