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    A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

    A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications von Vamvakos, Socrates D., Gauthier, Claude R., Rao, Chethan, Wang, Alvin, Canagasaby, Karthisha Ramoshan, Abugharbieh, Khaldoon, Choudhary, Prashant, Dabral, Sanjay, Desai, Shaishav, Hassan, Mahmudul, Hsieh, K. C., Kleveland, Bendik, Mandal, Gurupada, Rouse, Richard, Saraf, Ritesh, Yeung, Jason, Cao, Ying


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    A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

    A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications von Vamvakos, S. D., Gauthier, C. R., Rao, Chethan, Canagasaby, K. R., Choudhary, P., Dabral, S., Desai, S., Hassan, M., Hsieh, K. C., Kleveland, B., Mandal, G., Rouse, R., Saraf, R., Wang, A., Yeung, J., Abugharbieh, K., Ying Cao


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