LRTransDet: A Real-Time SAR Ship-Detection Network with Lightweight ViT and Multi-Scale Feature Fusion von Feng, Kunyu, Lun, Li, Wang, Xiaofeng, Cui, Xiaoxin

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A Comparative Study on the Performance and Security Evaluation of Spiking Neural Networks von Li, Yanjie, Cui, Xiaoxin, Zhou, Yihao, Li, Ying

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Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates von Cui, Xiaole, Ma, Xiao, Lin, Qiujun, Li, Xiang, Zhou, Hang, Cui, Xiaoxin

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High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ) von Liao, Kai, Cui, Xiaoxin, Liao, Nan, Wang, Tian, Yu, Dunshan, Cui, Xiaole

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An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias von Cui, Xiaole, Cui, Xiaoxin, Ni, Yewen, Miao, Min, Yufeng, Jin

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A Scatter-and-Gather Spiking Convolutional Neural Network on a Reconfigurable Neuromorphic Hardware von Zou, Chenglong, Cui, Xiaoxin, Kuang, Yisong, Liu, Kefei, Wang, Yuan, Wang, Xinan, Huang, Ru

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The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates von Cui, Xiaole, Ma, Ye, Wei, Feng, Cui, Xiaoxin

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Design of the RRAM-Based Polymorphic Look-Up Table Scheme von Cui, Xiaole, Li, Xiang, Zhang, Miaomiao, Cui, Xiaoxin

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A Hardware Implementation of SNN-Based Spatio-Temporal Memory Model von Liu, Kefei, Cui, Xiaoxin, Zhong, Yi, Kuang, Yisong, Wang, Yuan, Tang, Huajin, Huang, Ru

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Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array von Cui, Xiaole, Zhang, Miaomiao, Lin, Qiujun, Cui, Xiaoxin, Pang, Anqi

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Low power adiabatic logic based on FinFETs von Liao, Nan, Cui, XiaoXin, Liao, Kai, Ma, KaiSheng, Wu, Di, Wei, Wei, Li, Rui, Yu, DunShan

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Improving DFA attacks on AES with unknown and random faults von Liao, Nan, Cui, Xiaoxin, Liao, Kai, Wang, Tian, Yu, Dunshan, Cui, Xiaole

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Testing of 1TnR RRAM array with sneak path technique von Cui, Xiaole, Zhang, Qiang, Cui, Xiaoxin, Wang, Xinan, Kang, Jinfeng, Liu, Xiaoyan

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Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique von Wang, Tian, Cui, Xiaoxin, Ni, Yewen, Liao, Kai, Liao, Nan, Yu, Dunshan, Cui, Xiaole

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Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs von Liao, Kai, Cui, XiaoXin, Liao, Nan, Ma, KaiSheng, Wu, Di, Wei, Wei, Li, Rui, Yu, DunShan

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An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array von Zhang, Sunrui, Cui, Xiaole, Wei, Feng, Cui, Xiaoxin

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Leakage Power Reduction of Adiabatic Circuits Based on FinFET Devices von LIAO, Kai, CUI, XiaoXin, LIAO, Nan, MA, KaiSheng

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An Efficient Neuromorphic Implementation of Temporal Coding Based On-chip STDP Learning von Zhong, Yi, Wang, Zilin, Cui, Xiaoxin, Cao, Jian, Wang, Yuan

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OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support von Guo, Qingyu, Pan, Nanbing, Qiao, Xin, Cui, Xiaoxin, Wang, Yuan

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The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice von Chen, Yongliang, Cui, Xiaole, Cui, Xiaoxin, Zhang, Xing

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