A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor von Hwa-Joon Oh, Mueller, S.M., Jacobi, C., Tran, K.D., Cottier, S.R., Michael, B.W., Nishikawa, H., Totsuka, Y., Namatame, T., Yano, N., Machida, T., Dhong, S.H.

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Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V von Pille, J., Adams, C., Christensen, T., Cottier, S.R., Ehrenreich, S., Kono, F., Nelson, D., Takahashi, O., Tokito, S., Torreiter, O., Wagner, O., Wendel, D.

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Forced pulldown of array read bitlines for generating MUX select signals von ONISHI SHOHJI, COTTIER SCOTT R

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Level shifter for boosting wordline voltage and memory cell performance von JOSHI RAJIV V, PILLE JUERGEN, DHONG SANG HOO, TAKAHASHI OSAMU, COTTIER SCOTT R

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Level shifter for boosting wordline voltage and memory cell performance von Cottier, Scott R, Dhong, Sang Hoo, Joshi, Rajiv V, Pille, Juergen, Takahashi, Osamu

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Array read access control using MUX select signal gating of the read port von ONISHI SHOHJI, LIU PEICHUN P, COTTIER SCOTT R

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LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE von JOSHI RAJIV V, PILLE JUERGEN, DHONG SANG HOO, TAKAHASHI OSAMU, COTTIER SCOTT R

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A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor von Hwa-Joon Oh, Mueller, S.M., Jacobi, C., Tran, K.D., Cottier, S.R., Michael, B.W., Nishikawa, H., Totsuka, Y., Namatame, T., Yano, N., Machida, T., Dhong, S.H.

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Memory circuit and method for controlling cell voltage during memory operation von JOSHI RAJIV V, PILLE JUERGEN, DHONG SANG HOO, TAKAHASHI OSAMU, COTTIER SCOTT R

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