Merge : A Programming Model for Heterogeneous Multi-core Systems von LINDERMAN, Michael D, COLLINS, Jamison D, HONG WANG, MENG, Teresa H

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Helper threads via virtual multithreading von Wang, P.H., Collins, J.D., Dongkeun Kim, Greene, B., Kai-Ming Chan, Yunus, A.B., Sych, T., Moore, S.F., Shen, J.P., Wang, Hong

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Speculative precomputation: long-range prefetching of delinquent loads von Collins, Jamison D., Wang, Hong, Tullsen, Dean M., Hughes, Christopher, Lee, Yong-Fong, Lavery, Dan, Shen, John P.

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Runtime identification of cache conflict misses: The adaptive miss buffer von COLLINS, Jamison D, TULLSEN, Dean M

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Control Flow Optimization Via Dynamic Reconvergence Prediction von Collins, Jamison D., Tullsen, Dean M., Wang, Hong

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Hardware identification of cache conflict misses von Collins, J.D., Tullsen, D.M.

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CPR: Composable performance regression for scalable multiprocessor models von Lee, Benjamin C., Collins, Jamison, Wang, Hong, Brooks, David

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Pointer cache assisted prefetching von Collins, J., Sair, S., Calder, B., Tullsen, D.M.

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Bothnia: a dual-personality extension to the Intel integrated graphics driver von Chinya, Gautham N., Collins, Jamison D., Wang, Perry H., Jiang, Hong, Lueh, Guei-Yuan, Piazza, Thomas A., Wang, Hong

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Bothnia: A Dual-personality Extension to the Intel Integrated Graphics Driver : Systems Work at Intel von CHINYA, Gautham N, COLLINS, Jamison D, WANG, Perry H, HONG JIANG, LUEH, Guei-Yuan, PIAZZA, Thomas A, HONG WANG

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Speculative precomputation: long-range prefetching of delinquent loads von Collins, J.D., Wang, Hong, Tullsen, D.M., Hughes, C., Yong-Fong Lee, Lavery, D., Shen, J.P.

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EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system von Wang, Perry H., Collins, Jamison D., Chinya, Gautham N., Jiang, Hong, Tian, Xinmin, Girkar, Milind, Yang, Nick Y., Lueh, Guei-Yuan, Wang, Hong

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Merge: a programming model for heterogeneous multi-core systems von Linderman, Michael D., Collins, Jamison D., Wang, Hong, Meng, Teresa H.

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Runtime identification of cache conflict misses von Collins, Jamison D, Tullsen, Dean M

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Instruction and logic for predication and implicit destination von Chen, Howard, Collins, Jamison, Iyer, Jayesh, Winkel, Sebastian

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Fused adjacent memory stores von Collins, Jamison D, Sondag, Tyler, Winkel, Sebastian

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Multiple Instruction Stream Processor von Hankins, Richard A., Chinya, Gautham N., Collins, Jamison D., Wang, Perry H., Rakvic, Ryan, Wang, Hong, Shen, John P.

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Apparatuses and methods to prevent execution of a modified instruction von Agron, Jason M, Collins, Jamison D, Xekalakis, Polychronis

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FUSED ADJACENT MEMORY STORES von Sondag Tyler, Collins Jamison D, Winkel Sebastian

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Multiple Instruction Stream Processor von Hankins, Richard A, Chinya, Gautham N, Collins, Jamison D, Wang, Perry H, Rakvic, Ryan, Wang, Hong, Shen, John P

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