Random Dopant Fluctuation in Limited-Width FinFET Technologies von CHIANG, Meng-Hsueh, LIN, Jeng-Nan, KIM, Keunwoo, CHUANG, Ching-Te

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40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist von Chiu, Yi-Wei, Hu, Yu-Hao, Tu, Ming-Hsien, Zhao, Jun-Kai, Chu, Yuan-Hua, Jou, Shyh-Jye, Chuang, Ching-Te

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A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing von TU, Ming-Hsien, LIN, Jihi-Yu, CHUANG, Ching-Te, TSAI, Ming-Chien, LU, Chien-Yu, LIN, Yuh-Jiun, WANG, Meng-Hsueh, HUANG, Huan-Shun, LEE, Kuen-Di, SHIH, Wei-Chiang (willis), JOU, Shyh-Jye

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Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET von Ming-Long Fan, Hu, Vita Pi-Ho, Yin-Nein Chen, Pin Su, Ching-Te Chuang

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Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs von Yu, Chang-Hung, Su, Pin, Chuang, Ching-Te

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Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs von Yu, Chang-Hung, Su, Pin, Chuang, Ching-Te

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Novel Cu-to-Cu Bonding With Ti Passivation at 180 ^ in 3-D Integration von Huang, Yan-Pin, Chien, Yu-San, Tzeng, Ruoh-Ning, Shy, Ming-Shaw, Lin, Teu-Hua, Chen, Kou-Hua, Chiu, Chi-Tsung, Chiou, Jin-Chern, Chuang, Ching-Te, Hwang, Wei, Tong, Ho-Ming, Chen, Kuan-Neng

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High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices von Chiang, M.-H., Kim, K., Chuang, C.-T., Tretz, C.

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Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist von Hu, Vita Pi-Ho, Ming-Long Fan, Pin Su, Ching-Te Chuang

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Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist von Tu, Ming-Hsien, Lin, Jihi-Yu, Tsai, Ming-Chien, Jou, Shyh-Jye, Chuang, Ching-Te

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SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage von Mukhopadhyay, Saibal, Rao, Rahul M, Jae-Joon Kim, Ching-Te Chuang

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Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications von Chang-Hung Yu, Ming-Long Fan, Kuan-Chin Yu, Hu, Vita Pi-Ho, Pin Su, Ching-Te Chuang

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Design and Analysis of Robust Tunneling FET SRAM von Yin-Nien Chen, Ming-Long Fan, Hu, Vita Pi-Ho, Pin Su, Ching-Te Chuang

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Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET von Hu, Vita Pi-Ho, Ming-Long Fan, Pin Su, Ching-Te Chuang

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Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits von Fan, Ming-Long, Hu, Vita Pi-Ho, Chen, Yin-Nien, Su, Pin, Chuang, Ching-Te

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Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET von Ming-Long Fan, Hu, Vita Pi-Ho, Yin-Nien Chen, Chih-Wei Hsu, Pin Su, Ching-Te Chuang

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Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap von Lan Wei, Jie Deng, Li-Wen Chang, Keunwoo Kim, Ching-Te Chuang, Wong, H.-S.P.

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A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist von Wu, Shang-Lin, Li, Kuang-Yu, Huang, Po-Tsang, Hwang, Wei, Tu, Ming-Hsien, Lung, Sheng-Chi, Peng, Wei-Sheng, Huang, Huan-Shun, Lee, Kuen-Di, Kao, Yung-Shin, Chuang, Ching-Te

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An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem von Hu, Yu-Chen, Huang, Yu-Chieh, Huang, Po-Tsang, Wu, Shang-Lin, Chang, Hsiao-Chun, Yang, Yu-Tao, You, Yan-Huei, Chen, Jr-Ming, Huang, Yan-Yu, Lin, Yen-Han, Duann, Jeng-Ren, Chiu, Tzai-Wen, Hwang, Wei, Chuang, Ching-Te, Chiou, Jin-Chern, Chen, Kuan-Neng

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Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High- \kappa Metal-Gate Devices von YANG, Hao-I, HWANG, Wei, CHUANG, Ching-Te

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