ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols von Cho, Hyungmin

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Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects von Cho, Hyungmin

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Correction to "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects" von Cho, Hyungmin

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Correction to "ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols" von Cho, Hyungmin

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Generating Efficient Instruction Sequence for Software-Based Self-Testing of Processor Cores Using Reinforcement Learning von Seo, Jongseon, Cho, Hyungmin

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FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-sized Large Integers von Kang, Byeongmin, Cho, Hyungmin

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ERSA: Error Resilient System Architecture for Probabilistic Applications von Hyungmin Cho, Larkhoon Leem, Mitra, S.

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System-Level Effects of Soft Errors in Uncore Components von Hyungmin Cho, Cheng, Eric, Shepherd, Thomas, Chen-Yong Cher, Mitra, Subhasish

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Gallager B Decoder on Noisy Hardware von Sadegh Tabatabaei Yazdi, S. M., Hyungmin Cho, Dolecek, L.

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SpecMCTS: Accelerating Monte Carlo Tree Search Using Speculative Tree Traversal von Kim, Juhwan, Kang, Byeongmin, Cho, Hyungmin

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ERSA: Error Resilient System Architecture for probabilistic applications von Leem, Larkhoon, Hyungmin Cho, Bau, Jason, Jacobson, Quinn A, Mitra, Subhasish

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Optimal Water Backwashing Condition in Combined Water Treatment of Alumina Microfiltration and PP Beads von Cho, Hyungmin, Yoon, Gihoon, Kim, Minjae, Park, Jin Yong

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RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping von Cho, Hyungmin

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Sensitive Resource and Traffic Density Risk Analysis of Marine Spill Accidents Using Automated Identification System Big Data von Kim, Eunlak, Cho, Hyungmin, Kim, Namgyun, Kim, Eunjin, Ryu, Jewan, Park, Heekyung

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Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors von Jeong, Hyunjoon, Woo, Sangmin, Choi, Jinyoung, Cho, Hyungmin, Kim, Yohan, Kong, Jeong-Taek, Kim, Soyoung

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Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets von Cho, Hyungmin, Kwon, Kon-Woo

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Enhancement and Expansion of the Neural Network-Based Compact Model Using a Binning Method von Choi, JinYoung, Jeong, HyunJoon, Woo, SangMin, Cho, HyungMin, Kim, Yohan, Kong, Jeong-Taek, Kim, SoYoung

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Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) von Cheng, Eric, Mirkhani, Shahrzad, Szafaryn, Lukasz G., Chen-Yong Cher, Hyungmin Cho, Skadron, Kevin, Stan, Mircea R., Lilja, Klas, Abraham, Jacob A., Bose, Pradip, Mitra, Subhasish

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Quantitative evaluation of soft error injection techniques for robust system design von Cho, Hyungmin, Mirkhani, Shahrzad, Cher, Chen-Yong, Abraham, Jacob A., Mitra, Subhasish

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Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement von Pae, Sung-Il, Kozhikkottu, Vivek, Somasekar, Dinesh, Wu, Wei, Ramasubramanian, Shankar Ganesh, Dadual, Melin, Cho, Hyungmin, Kwon, Kon-Woo

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