Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- k Stacks von Kerber, A., Krishnan, S.A., Cartier, E.A.

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Pulse-Train Method to Measure Transient Response of Field-Effect Transistors von Jenkins, Keith A., Cartier, Eduard A., Yau, Jeng-Bang

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Origins of Effective Work Function Roll-Off Behavior for High-κ Last Replacement Metal Gate Stacks von Ando, Takashi, Cartier, Eduard A., Bruley, John, Choi, Kisik, Narayanan, Vijay

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Identification of structural phases in ferroelectric hafnium zirconium oxide by density-functional-theory-assisted EXAFS analysis von Sahiner, Mehmet Alper, Vander Valk, Rory J., Steier, Joshua, Savastano, Jared, Kelty, Stephen, Ravel, Bruce, Woicik, Joseph C., Ogawa, Yohei, Schmidt, Kristin, Cartier, Eduard A., Jordan-Sweet, Jean L., Lavoie, Christian, Frank, Martin M.

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On the Electron and Hole Tunneling in a HfO2 Gate Stack With Extreme Interfacial-Layer Scaling von ANDO, Takashi, SATHAYE, Ninad D, MURALI, Kota V. R. M, CARTIER, Eduard A

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A Fast Four-Point Sense Methodology for Extraction of Circuit-Relevant Degradation Parameters von Kerber, A, Cartier, E

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Evolution of interfacial Fermi level in In0.53Ga0.47As/high-κ/TiN gate stacks von Carr, Adra, Rozen, John, Frank, Martin M., Ando, Takashi, Cartier, Eduard A., Kerber, Pranita, Narayanan, Vijay, Haight, Richard

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Application of VRS Methodology for the Statistical Assessment of BTI in MG/HK CMOS Devices von Kerber, Andreas, Cartier, Eduard

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Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With HfO2/TiN Gate Stacks von KERBER, Andreas, MAITRA, Kingsuk, MAJUMDAR, Amlan, HARGROVE, Mike, CARTIER, Eduard Albert

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(Invited) The Past, Present and Future of High-k/Metal Gates von Choi, Kisik, Ando, Takashi, Cartier, Eduard A., Kerber, Andreas, Paruchuri, Vamsi, Iacoponi, John, Narayanan, Vijay

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Interfacial layer optimization of high- k/metal gate stacks for low temperature processing von Linder, Barry P., Narayanan, Vijay, Cartier, Eduard A.

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The Impact of Self-Heating on Charge Trapping in High-[Formula Omitted]-Metal-Gate nFETs von Khan, Faraz, Cartier, Eduard, Kothandaraman, Chandrasekara, Scott, J Campbell, Woo, Jason C S, Iyer, Subramanian S

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Oxygen defects and Fermi level location in metal-hafnium oxide-silicon structures von Lim, Daeyoung, Haight, Richard, Copel, Matthew, Cartier, Eduard

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Erratum: Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode von Dubourdieu, Catherine, Bruley, John, Arruda, Thomas M., Posadas, Agham, Jordan-Sweet, Jean, Frank, Martin M., Cartier, Eduard, Frank, David J., Kalinin, Sergei V., Demkov, Alexander A., Narayanan, Vijay

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Origins of Effective Work Function Roll-Off Behavior for High-[Formula Omitted] Last Replacement Metal Gate Stacks von Ando, Takashi, Cartier, Eduard A, Bruley, John, Choi, Kisik, Narayanan, Vijay

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Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With \hbox/\hbox Gate Stacks von Kerber, A., Maitra, K., Majumdar, A., Hargrove, M., Carter, R.J., Cartier, E.A.

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On the Electron and Hole Tunneling in a [Formula Omitted] Gate Stack With Extreme Interfacial-Layer Scaling von Ando, Takashi, Sathaye, Ninad D, Murali, Kota V. R. M, Cartier, Eduard A

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On the Electron and Hole Tunneling in a hbox HfO 2 Gate Stack With Extreme Interfacial-Layer Scaling von Ando, Takashi, Sathaye, Ninad D, Murali, Kota VRM, Cartier, Eduard A

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Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability von Frank, Martin M., Cartier, Eduard A., Ando, Takashi, Bedell, Stephen W., Bruley, John, Zhu, Yu, Narayanan, Vijay

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Interfacial layer optimization of high-@@ik@/metal gate stacks for low temperature processing von Linder, Barry P, Narayanan, Vijay, Cartier, Eduard A

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