A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations von Dias, Cesar de S., Marranghello, Felipe S., Brum, Raphael Martins, Butzen, Paulo F.

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A SPICE model for design of threshold current controlled memristive devices based applications von de Souza Dias, Cesar, Butzen, Paulo F.

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Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems von Balen, Tiago R., González, Carlos J., Oliveira, Ingrid F. V., da Rosa Jr, Leomar S., Soares, Rafael I., Schvittz, Rafael B., Added, Nemitala, Macchione, Eduardo L. A., Aguiar, Vitor A. P., Guazzelli, Marcilei A., Medina, Nilberto H., Butzen, Paulo F.

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BTI, HCI and TDDB aging impact in flip–flops von Nunes, Cícero, Butzen, Paulo F., Reis, André I., Ribas, Renato P.

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Efficient Memristive Stateful Logic Exploring Boolean Expressions in the Sum-of-Products Form von Dias, Cesar de S., de Lima, Helisa S., Brum, Raphael M., Butzen, Paulo F.

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Transistor network restructuring against NBTI degradation von Butzen, Paulo F., Bem, Vinícius Dal, Reis, André I., Ribas, Renato P.

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Optimizing machine learning logic circuits with constant signal propagation von Berndt, Augusto, Meinhardt, Cristina, Reis, Andre I., Butzen, Paulo F.

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Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits von Butzen, Paulo F., da Rosa, Leomar S., Chiappetta Filho, Erasmo J.D., Reis, André I., Ribas, Renato P.

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Routing Resistance Influence in Loading Effect on Leakage Analysis von Butzen, Paulo F., Reis, André I., Ribas, Renato P.

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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization von Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Fujita, Qingyang Yi Masahiro, Manske, Guilherme B, Pontes, Matheus F, Junior, Leomar S. da Rosa, de Aguiar, Marilton S, Butzen, Paulo F, Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R, Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z, de Abreu, Brunno A, Campos, Isac de Souza, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T, Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O, Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, Chatterjee, Satrajit

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Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates von Butzen, Paulo F., Reis, André I., Kim, Chris H., Ribas, Renato P.

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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization von Rai, Shubham, Walter Lau Neto, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Qingyang Yi Masahiro Fujita, Manske, Guilherme B, Pontes, Matheus F, Leomar S da Rosa Junior, de Aguiar, Marilton S, Butzen, Paulo F, Po-Chun Chien, Yu-Shan, Huang, Hoa-Ren, Wang, Jiang, Jie-Hong R, Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z, de Abreu, Brunno A, Isac de Souza Campos, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T, Mateus Grellert, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O, Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Pierre-Emmanuel Gaillardon, Mishchenko, Alan, Chatterjee, Satrajit

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Modeling Subthreshold Leakage Current in General Transistor Networks von Butzen, P.F., Reis, A.I., Kim, C.H., Ribas, R.P.

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Impact and optimization of lithography-aware regular layout in digital circuit design von Dal Bem, V., Butzen, P., Marranghello, F. S., Reis, A. I., Ribas, R. P.

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