A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology von Chakraborty, Sudipto, Frank, David J., Tien, Kevin, Rosno, Pat, Yeck, Mark, Glick, Joseph A., Robertazzi, Raphael, Richetta, Ray, Bulzacchelli, John F., Underwood, Devin, Ramirez, Daniel, Yilma, Dereje, Davies, Andrew, Joshi, Rajiv V., Chambers, Shawn D., Lekuch, Scott, Inoue, Ken, Wisnieff, Dorothy, Baks, Christian W., Bethune, Donald S., Timmerwilke, John, Fox, Thomas, Song, Peilin, Johnson, Blake R., Gaucher, Brian P., Friedman, Daniel J.

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Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS von Perez, Miguel E., Sperling, Michael A., Bulzacchelli, John F., Toprak-Deniz, Zeynep, Diemoz, Timothy E.

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A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS von Toprak-Deniz, Zeynep, Proesel, Jonathan E., Bulzacchelli, John F., Ainspan, Herschel A., Dickson, Timothy O., Beakes, Michael P., Meghelli, Mounir

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A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS von Proesel, Jonathan E., Toprak-Deniz, Zeynep, Cevrero, Alessandro, Ozkaya, Ilter, Kim, Seongwon, Kuchta, Daniel M., Lee, Sungjae, Rylov, Sergey V., Ainspan, Herschel, Dickson, Timothy O., Bulzacchelli, John F., Meghelli, Mounir

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A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links von Dickson, Timothy O., Deniz, Zeynep Toprak, Cochet, Martin, Beukema, Troy J., Kossel, Marcel, Morf, Thomas, Choi, Young-Ho, Francese, Pier Andrea, Brandli, Matthias, Baks, Christian W., Proesel, Jonathan E., Bulzacchelli, John F., Beakes, Michael P., Yoo, Byoung-Joo, Ahn, Hyoungbae, Lim, Dong-Hyuk, Kang, Gunil, Park, Sang-Hune, Meghelli, Mounir, Rhew, Hyo Gyuem, Friedman, Daniel J., Choi, Michael, Soyuer, Mehmet, Shin, Jongshin

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A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology von Bulzacchelli, J. F., Menolfi, C., Beukema, T. J., Storaska, D. W., Hertle, J., Hanson, D. R., Ping-Hsuan Hsieh, Rylov, S. V., Furrer, D., Gardellini, D., Prati, A., Morf, T., Sharma, V., Kelkar, R., Ainspan, H. A., Kelly, W. R., Chieco, L. R., Ritter, G. A., Sorice, J. A., Garlett, J. D., Callan, R., Brandli, M., Buchmann, P., Kossel, M., Toifl, T., Friedman, D. J.

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A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks von Rylyakov, Alexander, Proesel, Jonathan E., Rylov, Sergey, Lee, Benjamin G., Bulzacchelli, John F., Ardey, Abhijeet, Parker, Ben, Beakes, Michael, Baks, Christian W., Schow, Clint L., Meghelli, Mounir

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A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS von Agrawal, A., Bulzacchelli, J. F., Dickson, T. O., Liu, Y., Tierno, J. A., Friedman, D. J.

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A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology von Bulzacchelli, J.F., Meghelli, M., Rylov, S.V., Rhee, W., Rylyakov, A.V., Ainspan, H.A., Parker, B.D., Beakes, M.P., Aichin Chung, Beukema, T.J., Pepeljugoski, P.K., Shan, L., Kwark, Y.H., Gowda, S., Friedman, D.J.

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Errata - Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS" von Toprak-Deniz, Zeynep, Proesel, Jonathan E., Bulzacchelli, John F., Ainspan, Herschel A., Dickson, Timothy O., Beakes, Michael P., Meghelli, Mounir

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Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage von Bulzacchelli, J. F., Toprak-Deniz, Z., Rasmus, T. M., Iadanza, J. A., Bucossi, W. L., Seongwon Kim, Blanco, R., Cox, C. E., Chhabra, M., LeBlanc, C. D., Trudeau, C. L., Friedman, D. J.

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A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology von Dickson, T.O., Bulzacchelli, J.F., Friedman, D.J.

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An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects von Dickson, T. O., Yong Liu, Rylov, S. V., Bing Dang, Tsang, C. K., Andry, P. S., Bulzacchelli, J. F., Ainspan, H. A., Xiaoxiong Gu, Turlapati, L., Beakes, M. P., Parker, B. D., Knickerbocker, J. U., Friedman, D. J.

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A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology von Gangasani, G. R., Chun-Ming Hsu, Bulzacchelli, J. F., Rylov, S., Beukema, T., Freitas, D., Kelly, W., Shannon, M., Jieming Qi, Xu, H. H., Natonio, J., Rasmus, T., Jong-Ru Guo, Wielgos, M., Garlett, J., Sorna, M. A., Meghelli, M.

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A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE von Emami-Neyestanak, Azita, Varzaghani, Aida, Bulzacchelli, John F., Rylyakov, Alexander, Yang, Chih-Kong Ken, Friedman, Daniel J.

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A 1.8 pJ/bit 16 \times 16\;\text Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration von Dickson, Timothy O., Liu, Yong, Agrawal, Ankur, Bulzacchelli, John F., Ainspan, Herschel A., Toprak-Deniz, Zeynep, Parker, Benjamin D., Beakes, Michael P., Meghelli, Mounir, Friedman, Daniel J.

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Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate von Underwood, Devin, Glick, Joseph A., Inoue, Ken, Frank, David J., Timmerwilke, John, Pritchett, Emily, Chakraborty, Sudipto, Tien, Kevin, Yeck, Mark, Bulzacchelli, John F., Baks, Chris, Robertazzi, Raphael, Beck, Matthew, Joshi, Rajiv V., Wisnieff, Dorothy, Lekuch, Scott, Gaucher, Brian P., Friedman, Daniel J., Rosno, Pat, Ramirez, Daniel, Ruedinger, Jeff

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Superconducting VLSI Logic Cell Library Using DC-Powered Clockless Dynamic SFQ Gates and ASIC-Style Layout Template von Rylov, Sergey, Beck, Matthew, Tien, Kevin, Bulzacchelli, John, Wong, Mankit, Timmerwilke, John, Friedman, Daniel

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A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS von Byungsub Kim, Yong Liu, Dickson, T.O., Bulzacchelli, J.F., Friedman, D.J.

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Equalization for Electrical Links: Current Design Techniques and Future Directions von Bulzacchelli, John F.

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