A universal client for distributed networked design and computing von Brglez, Franc, Lavana, Hemang

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Fast true delay estimation during high level synthesis von Bhattacharya, S., Dey, S., Brglez, F.

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Transformations and resynthesis for testability of RT-level control-data path specifications von Bhattacharya, S., Brglez, F., Dey, S.

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Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking von Ghosh, D., Kapur, N., Harlow, J., Brglez, F.

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OpenDesign: an open user-configurable project environment for collaborative design and execution on the Internet von Lavana, H., Brglez, F., Reese, R., Konduri, G., Chandrakasan, A.

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Circuit partitioning for logic synthesis von Dey, S., Brglez, F., Kedem, G.

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Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications von Bhattacharya, S., Dey, S., Brglez, F.

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The scientific method and design and test von Brglez, F.

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A framework and method for hierarchical test generation von Calhoun, J.D., Brglez, F.

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Testability-Driven Random Test-Pattern Generation von Lisanke, R., Brglez, F., de Geus, A.J., Gregory, D.

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On SAT instance classes and a method for reliable performance experiments with SAT solvers von Brglez, Franc, Li, Xiao Yu, Stallmann, Matthias F.

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Clock Period Optimization During Resource Sharing and Assignment von Bhattacharya, S., Dey, S., Brglez, F.

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Automated synthesis for testability von Brglez, F., Bryan, D., Calhoun, J., Kedem, G., Lisanke, R.

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Characterization of Boolean functions for rapid matching in EPGA technology mapping von Schlichtmann, U., Brglez, F., Hermann, M.

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Effective bounding techniques for solving unate and binate covering problems von Xiao Yu Li, Stallmann, M.F., Brglez, F.

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A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation von Li, Xiao Yu, Stallmann, Matthias F., Brglez, Franc

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Effective bounding techniques for solving unate and binate covering problems von Li, Xiao Yu, Stallmann, Matthias F., Brglez, Franc

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Accelerated transition fault simulation von Schultz, M. H., Brglez, F.

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Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations von Harlow, Justin E., Brglez, Franc

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Executable workflows: a paradigm for collaborative design on the Internet von Lavana, Hemang, Khetawat, Amit, Brglez, Franc, Kozminski, Krzysztof

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