Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation von Doong, K.Y.-Y., Sunnys Hsieh, Sheng-Che Lin, Binson Shen, Jye-Yen Cheng, Ding-Ming Kwai, Hess, C., Weiland, L.H., Hsu, C.C.H.

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The short-loop process tuning & yield evaluation by using the addressable failure site test structures (AFS-TS) von Yih-Yuh Doong, K., Sunnys Hsieh, Sheng-Che Lin, Binson Shen, Hsu, C.C.-H.

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Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation von DOONG, Kelvin Yih-Yuh, HSIEH, Sunnys, LIN, Sheng-Che, SHEN, Binson, CHENG, Jye-Yen, KWAI, Ding-Ming, HESS, Christopher, WEILAND, Larg H, HSU, Charles Ching-Hsiang

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The role of test structures for yield enhancement and yield ramp-up: an example of adoptive yield enhancement (AYE): n/sup +//p-well junction leakage enhanced the abnormal leakage... von Doong, K.Y.Y., Binson Shen, Sunnys Hsieh, Sheng-che Lin, Hsu, C.C.-H.

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Scaling variance, invariance and prediction of design rule: from 0.25-/spl mu/m to 0.10-/spl mu/m nodes in the era of foundry manufacturing von Doong, K.Y.-Y., Ting, J.K., Sunnys Hsieh, Lin, S.C., Binson Shen, Guo, J.C., Young, K.L., Chen, I.C., Sun, J.Y.C., Wang, J.K.

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