Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison von Bharath Sreenivasulu, V., Aruna Kumari, N., Kola, Sekhar Reddy, Singh, Jawar, Li, Yiming

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Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective von Kumari, Neelam Aruna, Sreenivasulu, V. Bharath, Vijayvargiya, Vikas, Upadhyay, Abhishek Kumar, Ajayan, J., Uma, M.

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Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications von V., Bharath Sreenivasulu, Vadthiya, Narendar

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Analog and mixed circuit analysis of nanosheet FET at elevated temperatures von N, Aruna Kumari, V, Bharath Sreenivasulu, Singh, Jawar

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Spacer engineering on multi-channel FinFET for advanced wireless applications von Bharath Sreenivasulu, V., Bhandari, Sheetal, Prasad, M., Mani, Prashant, Subba Reddy, C., Durga Prakash, M.

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An intensive study on organic thin film transistors (OTFTs) for future flexible/wearable electronics applications von Ajayan, J., Sreejith, S., Manikandan, M., Bharath Sreenivasulu, V., Aruna Kumari, N., Ravindran, Ajith

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Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Impact of Scaling on Nanosheet FET and CMOS Circuit Applications von Kumari, N. Aruna, Sreenivasulu, V. Bharath, Prithvi, P.

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Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic... von Mounika, B., Ajayan, J., Bhattacharya, Sandip, Nirmal, D., Sreenivasulu, V. Bharath, Kumari, N. Aruna

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Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs von Sreenivasulu, V. Bharath, Kumari, N. Aruna, Lokesh, Vakkalakula, Ajayan, J., Uma, M., Vijayvargiya, Vikas

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Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes von Sreenivasulu, V. Bharath, Narendar, Vadthiya

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Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs von Sreenivasulu, V. Bharath, Kumari, N. Aruna, Lokesh, Vakkalakula, Vishvakarma, Santosh Kumar, Narendar, V.

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Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications von Kumari, N. Aruna, Vijayvargiya, Vikas, Upadhyay, Abhishek Kumar, Sreenivasulu, V. Bharath, Narendar, V., Prithvi, P.

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