Breakdown voltage improvement of standard MOS technologies targeted at smart power von Mendonca Santos, P., Castro Simas, M.I., Lanca, M., Finco, S., Behrens, F.H.

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Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis von da Silva, E.R., Costa, F., Behrens, F.H., Kickhofel, R.S., Maltione, R.

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Using mixed-mode test bus architecture to RF-based fault injection analysis and EMC fault debug von da Silva, E.R., Costa, F., Behrens, F.H., Kickhofel, R.S., Maltione, R.

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An approach for microsystems codesign von Ribas, R.P., Behrens, F.H.

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Smart power IC for DC-DC low power regulation von Finco, S., Behrens, F.H., Castro Simas, M.I.

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A monolithic smart switching cell targeted to a wide range of low power high density applications von Finco, S., Guilherme, J., Behrens, F.H., Simas, M.I.C.

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Modeling and characterization of LDD and LDSD NMOS transistors von Castro Simas, M.I., Costa Freire, J., Finco, S., Behrens, F.H.

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Methylation of L1RE1, RARB, and RASSF1 function as possible biomarkers for the differential diagnosis of lung cancer von Walter, R F H, Rozynek, P, Casjens, S, Werner, R, Mairinger, F D, Speel, E J M, Zur Hausen, A, Meier, S, Wohlschlaeger, J, Theegarten, D, Behrens, T, Schmid, K W, Brüning, T, Johnen, G

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