Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling von Bayrakci, Alp Arslan

Volltext

BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register Allocation von Terci, Gizem Sungu, Abdulhalik, Enes, Bayrakci, Alp Arslan, Boz, Betul

Volltext

Delay based hardware Trojan detection exploiting spatial correlations to suppress variations von Esirci, Fatma Nur, Bayrakci, Alp Arslan

Volltext

FPGA Based Low Cost Automatic Test Equipment for Digital Circuits von Bayrakci, Alp Arslan

Volltext

Stochastic logical effort as a variation aware delay model to estimate timing yield von Bayrakci, Alp Arslan

Volltext

Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation von Bayrakci, Alp Arslan, Demir, Alper, Tasiran, Serdar

Volltext

Acceleration of Spatial Correlation Based Hardware Trojan Detection Using Shared Grids Ratio von Esirci, Fatma Nur, Bayrakci, Alp Arslan

Volltext

Reduced Delay BCD Adder von Bayrakci, A.A., Akkas, A.

Volltext

Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE) von Bayrakci, Alp Arslan, Demir, Alper, Tasiran, Serdar

Volltext bestellen

Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE) von Alp Arslan Bayrakci, Demir, Alper, Tasiran, Serdar

Volltext