Reducing LUT Count for Mealy FSMs With Transformation of States von Barkalov, Alexander A., Titarenko, Larysa, Mielcarek, Kamil

Volltext

Improving characteristics of LUT-based Mealy FSMs von Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil

Volltext

Reducing the Number of Luts for Mealy FSMS with State Transformation von Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil

Volltext

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections von Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata

Volltext

Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems von Barkalov, Alexander, Titarenko, Larysa, Krzywicki, Kazimierz

Volltext

Hardware Reduction for Lut–Based Mealy FSMs von Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil

Volltext

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review von Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Krzywicki, Kazimierz

Volltext

Improving Characteristics of FPGA-Based FSMs Representing Sequential Blocks of Cyber-Physical Systems von Barkalov, Alexander, Titarenko, Larysa, Krzywicki, Kazimierz, Saburova, Svetlana

Volltext

Hardware reduction for FSMs with extended state codes von Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Malgorzata

Volltext

Optimization of a Mealy Automaton Circuit in a Mixed Element Basis von Barkalov, Alexander, Titarenko, Larysa, Golovin, Oleksandr, Matvienko, Oleksandr

Volltext

Improving Characteristics of FSMs With Mixed Codes of Outputs von Barkalov, Alexander, Titarenko, Larysa, Chmielewski, Slawomir, Mielcarek, Kamil

Volltext

Improving Hardware in LUT-Based Mealy FSMs von Barkalov, Alexander, Titarenko, Larysa, Krzywicki, Kazimierz

Volltext

Solving Load Balancing Problems in Routing and Limiting Traffic at the Network Edge von Barkalov, Alexander, Lemeshko, Oleksandr, Yeremenko, Oleksandra, Titarenko, Larysa, Yevdokymenko, Maryna

Volltext

Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores von Titarenko, Larysa, Kharchenko, Vyacheslav, Puidenko, Vadym, Perepelitsyn, Artem, Barkalov, Alexander

Volltext

Reducing LUT Count for FPGA-Based Mealy FSMs von Barkalov, Alexander, Titarenko, Larysa, Krzywicki, Kazimierz

Volltext

Improving characteristics of LUT-based Moore FSMs von Barkalov, Alexander, Titarenko, Larysa, Chmielewski, Slawomir

Volltext

Optimization of a Moore Automaton Circuit in a Mixed Element Basis von Barkalov, Alexander, Titarenko, Larysa, Golovin, Oleksandr, Matvienko, Oleksandr

Volltext

Improving LUT count of FPGA-based sequential blocks von Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Krzywicki, Kazimierz

Volltext

Encoding of Terms in EMB-Based Mealy FSMs von Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Krzywicki, Kazimierz

Volltext

Foundations of Embedded Systems von Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata

Volltext