Architecture of an image signal processor von Fukushima, Tadashi, Kobayashi, Yoshiki, Hirasawa, Kohtaroh, Bandoh, Tadaaki, Ejiri, Masakazu

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5404472 Parallel processing apparatus and method capable of switching parallel and successive processing modes von Kenichi, Kurosawa, Shigeya, Tanaka, Yasuhiro, Nakatsuka, Tadaaki, Bandoh

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Multi-processor system having a multi-port cache memory von BANDOH, TADAAKI

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MULTI-PROCESSOR SYSTEM HAVING A MULTI-PORT CACHE MEMORY von BANDOH, TADAAKI

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MULTI-PROCESSOR SYSTEM HAVING A MULTI-PORT CACHE MEMORY von BANDOH, TADAAKI

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Multi-processor system having a multi-port cache memory von BANDOH, TADAAKI

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3.3-V BiCMOS circuit techniques for a 120-MHz RIAC microprocessor von Murabayashi, Fumio, Hotta, Takashi, Tanaka, Shigeya, Yamauchi, Tatsumi, Yamada, Hiromichi, Nakano, Tetsuo, Kobayashi, Yutaka, Bandoh, Tadaaki

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MULTI-PROCESSOR SYSTEM HAVING A MULTI-PORT CACHE MEMORY von BANDOH, TADAAKI

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Multi-processor system having a multi-port cache memory von BANDOH, TADAAKI

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3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor von Murabayashi, F., Hotta, T., Tanaka, S., Yamauchi, T., Yamada, H., Nakano, T., Kobayashi, Y., Bandoh, T.

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1.3- mu m CMOS/bipolar standard cell library for VLSI computers von Hotta, T., Kurita, K., Maejima, H., Iwamura, M., Tanaka, S., Bandoh, T., Yamauchi, T., Hotta, A.

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Data processing system with processors having different processing speeds sharing a common bus von BANDOH, TADAAKI, FUKUNAGA, YASUSHI

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Control of instruction pipeline in data processing system von BANDOH, TADAAKI, FUKUNAGA, YASUSHI

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Address conversion unit for data processing system von BANDOH, TADAAKI, FUKUNAGA, YASUSHI

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Logical cache memory for multi-processor system von BANDOH, TADAAKI, MORIOKA, MICHIO, TANJI, MASAYUKI

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Information processor and information processing system utilizing interface for synchronizing clock signal von IWAMURA MASAHIRO, SINODA SIN-ICHI, BANDOH TADAAKI, TANAKA SHIGEYA, KATO KAZUO, NAKATSUKA YASUHIRO, KURITA KOZABURO, MAEJIMA HIDEO, HOTTA TAKASHI

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Information processor and information processing system utilizing interface for synchronizing clock signal von Hotta, Takashi, Kurita, Kozaburo, Iwamura, Masahiro, Maejima, Hideo, Tanaka, Shigeya, Bandoh, Tadaaki, Nakatsuka, Yasuhiro, Kato, Kazuo, Sinoda, Sin-ichi

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Parallel processing apparatus and parallel processing method von KUROSAWA, KENICHI, BANDOH, TADAAKI, TANAKA, SHIGEYA, NAKATSUKA, YASUHIRO

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A 120-MHz BiCMOS superscalar RISC processor von Tanaka, S., Hotta, T., Murabayashi, F., Yamada, H., Yoshida, S., Shimamura, K., Katsura, K., Bandoh, T., Ikeda, K., Matsubara, K., Saitou, K., Nakano, T., Shimizu, T., Satomura, R.

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Parallel processing apparatus and method capable of processing plural instructions in parallel or successively von BANDOH, TADAAKI, TANAKA, SHIGEYA, KUROSAWA, KENICHI, NAKATSUKA, YASUHIRO

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