Memory Systems - Cache, DRAM, Disk von Jacob, Bruce, Wang, David, Ng, Spencer

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DRAM Refresh Mechanisms, Penalties, and Trade-Offs von Bhati, Ishwar, Mu-Tien Chang, Chishti, Zeshan, Shih-Lien Lu, Jacob, Bruce

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Fine-Grained Activation for Power Reduction in DRAM von Cooper-Balis, Elliott, Jacob, Bruce

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A role for the CXCR4-CXCL12 axis in the little skate, Leucoraja erinacea von Hersh, Taylor A, Dimond, Alexandria L, Ruth, Brittany A, Lupica, Noah V, Bruce, Jacob C, Kelley, John M, King, Benjamin L, Lutton, Bram V

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Ransomware Classification Using Hardware Performance Counters on a Non-Virtualized System von Hill, Jennie E., Owens Walker, T., Blanco, Justin A., Ives, Robert W., Rakvic, Ryan, Jacob, Bruce

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The Gideon trials von Jacob, Bruce R

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Editor-in-Chief von Abbott, Derek, Aissa, Sonia, Annaswamy, Anuradha, Ansari, Nirwan, Cai, Jun, Chen, Kun-Shan, Chen, Yixin, Chiao, J.-C., El-Baz, Ayman, Fattah, Shaikh, Gooi, Hoay, Gokhale, Maya, I, Chih-Lin, Iannaccone, Giuseppe, Iwashita, Yumi, Jacob, Bruce, Jamalipour, Abbas, Javidi, Bahram, Jiang, Weihua, Kaynak, Okyay, Kirkici, Hulya, Lambert-Torres, Germano, Li, Shengtao, Mrozowski, Michal, Nappi, Michele, Novak, Dalma, Proenca, Hugo, Qian, Yi, Qu, Zhihua, Rahardja, Susanto, Saif, Mehrdad, Serpenguzel, Ali, Siegel, Peter H., Trebi-Ollennu, Ashitey, Tuninetti, Daniela, Wang, Ge, Wear, Keith A., Weisshaar, Andreas, Yue, C. Patrick, Zio, Enrico

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DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator von Li, Shang, Yang, Zhiyuan, Reddy, Dhiraj, Srivastava, Ankur, Jacob, Bruce

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The 2 PetaFLOP, 3 Petabyte, 9 TB/s, 90 kW Cabinet: A System Architecture for Exascale and Big Data von Jacob, Bruce

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DRAMSim2: A Cycle Accurate Memory System Simulator von Rosenfeld, P, Cooper-Balis, E, Jacob, B

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Memory Systems von Bruce Jacob, Spencer Ng, David Wang

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The Case for VLIW-CMP as a Building Block for Exascale von Jacob, Bruce

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Belzutifan for Renal Cell Carcinoma in von Hippel–Lindau Disease von Jonasch, Eric, Donskov, Frede, Iliopoulos, Othon, Rathmell, W. Kimryn, Narayan, Vivek K, Maughan, Benjamin L, Oudard, Stephane, Else, Tobias, Maranchie, Jodi K, Welsh, Sarah J, Thamake, Sanjay , Park, Eric K, Perini, Rodolfo F, Linehan, W. Marston, Srinivasan, Ramaprasad

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Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM von Mu-Tien Chang, Rosenfeld, P., Shih-Lien Lu, Jacob, B.

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Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die von Jagasivamani, Meenatchi, Walden, Candace, Singh, Devesh, Kang, Luyi, Li, Shang, Asnaashari, Mehdi, Dubois, Sylvain, Jacob, Bruce, Yeung, Donald

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Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache von Walden, Candace, Singh, Devesh, Jagasivamani, Meenatchi, Li, Shang, Kang, Luyi, Asnaashari, Mehdi, Dubois, Sylvain, Jacob, Bruce, Yeung, Donald

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Using Many Small 1T1C Memory Arrays in a Large and Dense Multicore Processor von Carlstedt, Gunnar, Rimborg, Mats

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Algorithmic composition as a model of creativity von JACOB, BRUCE L.

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Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling von Bhati, Ishwar, Chishti, Zeshan, Jacob, Bruce

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Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm) von Rodriguez, Samuel, Jacob, Bruce

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