Optimizing the hot carrier reliability of N-LDMOS transistor arrays von Brisbin, Douglas, Strachan, Andy, Chaparala, Prasad

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Impact of NBTI and HCI on PMOSFET threshold voltage drift: Negative-Bias-Temperature Instability (NBTI) in MOS devices special sectio n von CHAPARALA, Prasad, BRISBIN, Douglas

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Impact of NBTI and HCI on PMOSFET threshold voltage drift von Chaparala, Prasad, Brisbin, Douglas

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Influence of test techniques on soft breakdown detection in ultra-thin oxides von Brisbin, Douglas, Chaparala, Prasad

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Photo Misalignment Impact on the Hot Carrier Reliability of Lateral DMOS Devices von Brisbin, D., Lindorfer, P., Chaparala, P.

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Effect of Photo Misalignment on N-LDMOS Hot Carrier Device Reliability von Brisbin, D., Lindorfer, P., Chaparala, P.

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Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications von Brisbin, D., Strachan, A., Chaparala, P.

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Anomalous NMOSFET hot carrier degradation due to trapped positive charge in a DGO CMOS process von Brisbin, D., Mirgorodski, Y., Chaparala, P.

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Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in von BRISBIN DOUGLAS, STRACHAN ANDREW

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Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in von Brisbin, Douglas, Strachan, Andrew

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Anomalous NMOSFET hot carrier degradation due to hole injection in a DGO CMOS process von Brisbin, D., Mirgorodski, Y., Chaparala, P.

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Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays von Brisbin, Douglas, Chaparala, Prasad

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Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays von BRISBIN DOUGLAS, CHAPARALA PRASAD

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Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in von BRISBIN DOUGLAS, STRACHAN ANDREW

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Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in von Brisbin, Douglas, Strachan, Andrew

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Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in von BRISBIN DOUGLAS, STRACHAN ANDREW

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Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in von BRISBIN DOUGLAS, STRACHAN ANDREW

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Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions von Strachan, Andy, Brisbin, Douglas

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Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions von BRISBIN DOUGLAS, STRACHAN ANDY

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PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in and method for designing and manufacturing such device von BRISBIN DOUGLAS, STRACHAN ANDREW

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