TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip von Akopyan, Filipp, Sawada, Jun, Cassidy, Andrew, Alvarez-Icaza, Rodrigo, Arthur, John, Merolla, Paul, Imam, Nabil, Nakamura, Yutaka, Datta, Pallab, Gi-Joon Nam, Taba, Brian, Beakes, Michael, Brezzo, Bernard, Kuang, Jente B., Manohar, Rajit, Risk, William P., Jackson, Bryan, Modha, Dharmendra S.

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A million spiking-neuron integrated circuit with a scalable communication network and interface von Merolla, Paul A., Arthur, John V., Alvarez-Icaza, Rodrigo, Cassidy, Andrew S., Sawada, Jun, Akopyan, Filipp, Jackson, Bryan L., Imam, Nabil, Guo, Chen, Nakamura, Yutaka, Brezzo, Bernard, Vo, Ivan, Esser, Steven K., Appuswamy, Rathinakumar, Taba, Brian, Amir, Arnon, Flickner, Myron D., Risk, William P., Manohar, Rajit, Modha, Dharmendra S.

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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons von Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., Friedman, D. J.

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A Hardware/Software Approach for Database Query Acceleration with FPGAs von Sukhwani, Bharat, Thoennes, Mathew, Min, Hong, Dube, Parijat, Brezzo, Bernard, Asaad, Sameh, Dillenberger, Donna

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Database Analytics: A Reconfigurable-Computing Approach von Sukhwani, Bharat, Hong Min, Thoennes, Mathew, Dube, Parijat, Brezzo, Bernard, Asaad, Sameh, Dillenberger, Donna Eng

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Large Payload Streaming Database Sort and Projection on FPGAs von Sukhwani, Bharat, Thoennes, Mathew, Hong Min, Dube, Parijat, Brezzo, Bernard, Asaad, Sameh, Dillenberger, Donna

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Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface von Merolla, Paul A, Arthur, John V, Alvarez-Icaza, Rodrigo, Cassidy, Andrew S, Sawada, Jun, Akopyan, Filipp, Jackson, Bryan L, Imam, Nabil, Guo, Chen, Nakamura, Yutaka, Brezzo, Bernard, Vo, Ivan, Esser, Steven K, Appuswamy, Rathinakumar, Taba, Brian, Amir, Arnon, Flickner, Myron D, Risk, William P, Manohar, Rajit, Modha, Dharmendra S

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Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network von Brezzo, Bernard V, Seo, Jae-sun, Friedman, Daniel J, Tierno, Jose A, Chang, Leland, Merolla, Paul A, Arthur, John V, Montoye, Robert K, Modha, Dharmendra S

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Increasing throughput of multiplexed electrical bus in pipe-lined architecture von BREZZO BERNARD V, ASAAD SAMEH, KAPUR MOHIT

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Reconfigurable and customizable general-purpose circuits for neural networks von Esser, Steven K, Liu, Yong, Brezzo, Bernard V, Seo, Jae-sun, Friedman, Daniel J, Rajendran, Bipin, Tierno, Jose A, Chang, Leland, Montoye, Robert K, Modha, Dharmendra S

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TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK von Brezzo, Bernard V, Seo, Jae-sun, Friedman, Daniel J, Tierno, Jose A, Chang, Leland, Merolla, Paul A, Arthur, John V, Montoye, Robert K, Modha, Dharmendra S

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Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network von Brezzo, Bernard V, Seo, Jae-sun, Friedman, Daniel J, Tierno, Jose A, Chang, Leland, Merolla, Paul A, Arthur, John V, Montoye, Robert K, Modha, Dharmendra S

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INCREASING THROUGHPUT OF MULTIPLEXED ELECTRICAL BUS IN PIPE-LINED ARCHITECTURE von BREZZO BERNARD V, ASAAD SAMEH, KAPUR MOHIT

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High-Throughput, Lossless Data Compresion on FPGAs von Sukhwani, B, Abali, B, Brezzo, B, Asaad, S

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Single-chip 4×500-MBd CMOS transceiver von Widmer, A.X., Wrenner, K., Ainspan, H.A., Parker, B., Austruy, P., Brezzo, B., Haen, A.-M., Ewen, J.F., Soyuer, M., Blanc, A., Abbiate, J.-C., Deutsch, A., Hyun J. Shin

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Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation von Friedman Daniel J, Brezzo Bernard V, Arthur John V, Tierno Jose A, Chang Leland, Montoye Robert K, Modha Dharmendra S, Merolla Paul A, Seo Jae-sun

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RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS von Rajendran Bipin, Friedman Daniel J, Brezzo Bernard V, Liu Yong, Tierno Jose A, Chang Leland, Montoye Robert K, Modha Dharmendra S, Esser Steven K, Seo Jae-sun

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RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS von Rajendran Bipin, Friedman Daniel J, Brezzo Bernard V, Liu Yong, Tierno Jose A, Chang Leland, Montoye Robert K, Modha Dharmendra S, Esser Steven K, Seo Jae-sun

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Reconfigurable and customizable general-purpose circuits for neural networks von Rajendran Bipin, Friedman Daniel J, Brezzo Bernard V, Liu Yong, Tierno Jose A, Chang Leland, Montoye Robert K, Modha Dharmendra S, Esser Steven K, Seo Jae-sun

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TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION von Friedman Daniel J, Brezzo Bernard V, Arthur John V, Tierno Jose A, Chang Leland, Montoye Robert K, Modha Dharmendra S, Merolla Paul A, Seo Jae-sun

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