CMOS Scaling Trends and Beyond von Bohr, Mark T., Young, Ian A.

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Nanotechnology goals and challenges for electronic applications von Bohr, M.T.

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The evolution of scaling from the homogeneous era to the heterogeneous era von Bohr, M.

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Why Gen Y are leaving Hillsong and other Pentecostal churches von Mark Bohr, Philip Hughes

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The new era of scaling in an SoC world von Bohr, M.

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A 90-nm logic technology featuring strained-silicon von Thompson, S.E., Armstrong, M., Auth, C., Alavi, M., Buehler, M., Chau, R., Cea, S., Ghani, T., Glass, G., Hoffman, T., Jan, C.-H., Kenyon, C., Klaus, J., Kuhn, K., Zhiyong Ma, Mcintyre, B., Mistry, K., Murthy, A., Obradovic, B., Nagisetty, R., Phi Nguyen, Sivakumar, S., Shaheed, R., Shifren, L., Tufts, B., Tyagi, S., Bohr, M., El-Mansy, Y.

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A logic nanotechnology featuring strained-silicon von Thompson, S.E., Armstrong, M., Auth, C., Cea, S., Chau, R., Glass, G., Hoffman, T., Klaus, J., Zhiyong Ma, Mcintyre, B., Murthy, A., Obradovic, B., Shifren, L., Sivakumar, S., Tyagi, S., Ghani, T., Mistry, K., Bohr, M., El-Mansy, Y.

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Diffusion of copper through dielectric films under bias temperature stress von Raghavan, Gopal, Chiang, Chien, Anders, Paul B., Tzeng, Sing-Mo, Villasol, Reynaldo, Bai, Gang, Bohr, Mark, Fraser, David B.

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A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply von Kevin Zhang, Bhattacharya, U., Zhanping Chen, Hamzaoglu, F., Murray, D., Vallepalli, N., Yih Wang, Bo Zheng, Bohr, M.

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A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry von Karl, E., Yih Wang, Yong-Gee Ng, Zheng Guo, Hamzaoglu, F., Meterelliyoz, M., Keane, J., Bhattacharya, U., Zhang, K., Mistry, K., Bohr, M.

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In search of "Forever," continued transistor scaling one new material at a time von Thompson, S.E., Chau, R.S., Ghani, T., Mistry, K., Tyagi, S., Bohr, M.T.

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SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction von Zhang, K., Bhattacharya, U., Zhanping Chen, Hamzaoglu, F., Murray, D., Vallepalli, N., Yih Wang, Zheng, B., Bohr, M.

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A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management von Yih Wang, Bhattacharya, U., Hamzaoglu, F., Kolar, P., Yong-Gee Ng, Liqiong Wei, Ying Zhang, Zhang, K., Bohr, M.

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A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology von Hamzaoglu, F., Zhang, K., Yih Wang, Ahn, H.J., Bhattacharya, U., Zhanping Chen, Yong-Gee Ng, Pavlov, A., Smits, K., Bohr, M.

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A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications von YIH WANG, HONG JO AHN, LIN, Jie-Feng, NG, Yong-Gee, POST, Ian, LIQIONG WEI, YING ZHANG, ZHANG, Kevin, BOHR, Mark, BHATTACHARYA, Uddalak, ZHANPING CHEN, COAN, Tom, HAMZAOGLU, Fatih, HAFEZ, Walid M, JAN, Chia-Hong, KOLAR, Pramod, KULKARNI, Sarvesh H

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A 30 Year Retrospective on Dennard's MOSFET Scaling Paper von Bohr, Mark

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SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS von Bohr, Mark T

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REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN von BOHR, Mark T

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Technology for advanced high-performance microprocessors von Bohr, M.T., El-Mansy, Y.A.

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SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS von BOHR, Mark T

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