Practical Randomness Effects on Physical Security in Second-Order Threshold Implementation of AES von TSUKAHARA, Maki, HARADA, Yusaku, HIRATA, Haruka, MIYAHARA, Daiki, LI, Yang, HARA-AZUMI, Yuko, SAKIYAMA, Kazuo

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Approximate Data Reuse-based Accelerator Design for Embedded Processor von Osawa, Hisashi, Hara-Azumi, Yuko

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Implementation of Lightweight eHealth Applications on a Low-Power Embedded Processor von Yang, Mingyu, Hara-Azumi, Yuko

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Multimodal Neural Network Acceleration on a Hybrid CPU-FPGA Architecture: A Case Study von Trabelsi Ajili, Mehdi, Hara-Azumi, Yuko

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FPGA-based Hardware/Software Co-design of a Bio-inspired SAT Solver von Nguyen, Anh Hoang Ngoc, Aono, Masashi, Hara-Azumi, Yuko

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APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators von Achararit, Paniti, Hanif, Muhammad Abdullah, Putra, Rachmad Vidya Wicaksana, Shafique, Muhammad, Hara-Azumi, Yuko

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Real-Time Reconfiguration of Time-Aware Shaper for ULL Transmission in Dynamic Conditions von Nakayama, Yu, Yaegashi, Ryo, Nguyen, Anh Hoang Ngoc, Hara-Azumi, Yuko

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The Limits of SEMA on Distinguishing Similar Activation Functions of Embedded Deep Neural Networks von Takatoi, Go, Sugawara, Takeshi, Sakiyama, Kazuo, Hara-Azumi, Yuko, Li, Yang

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A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers von YAMAMOTO, Takahiro, TANIGUCHI, Ittetsu, TOMIYAMA, Hiroyuki, YAMASHITA, Shigeru, HARA-AZUMI, Yuko

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Hardware/Software Codesign of Real-Time Intrusion Detection System for Internet of Things Devices von Zeng, Qingyu, Hara-Azumi, Yuko

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Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs von TANIGUCHI, Ittetsu, KAIDA, Junya, HIEDA, Takuji, HARA-AZUMI, Yuko, TOMIYAMA, Hiroyuki

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Revisiting Simple and Energy Efficient Embedded Processor Designs Toward the Edge Computing von Saso, Kaoru, Hara-Azumi, Yuko

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Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs von KAIDA, Junya, HARA-AZUMI, Yuko, HIEDA, Takuji, TANIGUCHI, Ittetsu, TOMIYAMA, Hiroyuki, INOUE, Koji

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Selective Check of Data-Path for Effective Fault Tolerance von AHMED, Tanvir, YAO, Jun, HARA-AZUMI, Yuko, YAMASHITA, Shigeru, NAKASHIMA, Yasuhiko

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Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications von Pilato, Christian, Fang, Zhenman, Hara-Azumi, Yuko, Hwang, Jim

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自閉症スペクトラム障害における日本版WISC-IVの認知プロフィール: Cattell-Horn-Carroll 理論によるサブタイプの検討 von 岡田, 智, 飯利, 知恵子, 安住, ゆう子, 大谷, 和大

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SSA-AC: Static Significance Analysis for Approximate Computing von Metwalli, Sara Ayman, Hara-Azumi, Yuko

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Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs von Hara-Azumi, Yuko, Matsuba, Toshinobu, Tomiyama, Hiroyuki, Honda, Shinya, Takada, Hiroaki

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Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips von DINH, Trung Anh, YAMASHITA, Shigeru, HO, Tsung-Yi, HARA-AZUMI, Yuko

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Hardware/Software Cooperative Design Against Power Side-Channel Attacks on IoT Devices von Yang, Mingyu, Ahmed, Tanvir, Inagaki, Saya, Sakiyama, Kazuo, Li, Yang, Hara-Azumi, Yuko

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