Modified stable Euler-number algorithm implementation for real-time image binarization von Abbasi, Naeem, Athow, Jacques, Amer, Aishy

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Modified stable Euler-number algorithm implementation for real-time image binarization: Design and Architectures of Real-Time Image Processing in Embedded Systems von ABBASI, Naeem, ATHOW, Jacques, AMER, Aishy

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Real-time FPGA architecture of modified Stable Euler-Number algorithm for image binarization von Abbasi, N., Athow, J., Amer, A.

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A CNFET-based characterization framework for digital circuits von Athow, J. L., Rozon, C., Al-Khalili, D., Langlois, J. M. P.

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Implementation of large-integer hardware multiplier in Xilinx FPGA von Athow, J.L., Al-Khalili, A.J.

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Placement algorithm for multiplier-based FPGA circuits von Athow, J.L., Al-Khalili, A.J.

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