Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm von Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra

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Speed optimal FPGA implementation of the encryption algorithms for telecom applications von Sikka, Prateek, Asati, Abhijit R, Shekhar, Chandra

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Retraction Note to: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications von Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra

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Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications von Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra

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Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis von Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra

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Lightweight convolutional neural network architecture implementation using TensorFlow lite von Pandey, Jyoti, Asati, Abhijit R.

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High‐speed and area‐efficient Sobel edge detector on field‐programmable gate array for artificial intelligence and machine learning applications von Sikka, Prateek, Asati, Abhijit R, Shekhar, Chandra

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High-Level synthesis assisted design and verification framework for automotive radar processors von Sikka, Prateek, Asati, Abhijit R, Shekhar, Chandra

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RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications von Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra

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Dedicated hardware architecture for localizing iris in VW images von Kumar, Vineet, Asati, Abhijit, Gupta, Anu

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Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images von Kumar, Vineet, Asati, Abhijit, Gupta, Anu

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A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images von Kumar, Vineet, Gupta, Anu, Asati, Abhijit

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Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region von Gupta, Priya, Asati, Abhijit, Gupta, Anu

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A Novel Redundant Binary Number to Natural Binary Number Converter von Sahoo, S. K., Gupta, Anu, Asati, Abhijit R., Shekhar, Chandra

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Low-latency median filter core for hardware implementation of 5 × 5 median filtering von Kumar, Vineet, Asati, Abhijit, Gupta, Anu

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Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation von Kumar, Vineet, Asati, Abhijit, Gupta, Anu

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Hardware Accelerators for Iris Localization von Kumar, Vineet, Asati, Abhijit, Gupta, Anu

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Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images von Kumar, Vineet, Asati, Abhijit, Gupta, Anu

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Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems von Mishra, Ashish, Agarwal, Mohit, Asati, Abhijit Rameshwar, Raju, Kota Solomon

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Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images von Kumar, Vineet, Asati, Abhijit, Gupta, Anu

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