Design and optimization of multithreshold CMOS (MTCMOS) circuits von Anis, M., Areibi, S., Elmasry, M.

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The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study von Savich, A.W., Moussa, M., Areibi, S.

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Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm” von Ahmed, O., Grewal, G., Areibi, Shawki

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Corrigendum to “PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability” von Chattha, K., Areibi, Shawki, Ahmed, O., Kelly, B.

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Corrigendum to “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization” von Collier, R., Areibi, Shawki, Ahmed, O., Grewal, G.

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StarPlace: A new analytic method for FPGA placement von Xu, M., Grewal, G., Areibi, S.

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An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems von Wattar, A. Al, Areibi, S, Grewal, G

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Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm von Ahmed, O., Areibi, Shawki, Grewal, G.

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An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization von Grewal, G., Areibi, Shawki, Ahmed, O., Collier, R.

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An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C von Walton, M., Ahmed, O., Grewal, G., Areibi, S.

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PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability von Ahmed, O., Areibi, Shawki, Chattha, K., Kelly, B.

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Near-linear wirelength estimation for FPGA placement von Xu, M, Grewal, G, Areibi, S, Obimbo, C, Banerji, D

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Hierarchical FPGA placement von Areibi, S., Grewal, G., Banerji, D., Du, P.

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Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique von Anis, M., Areibi, S., Mahmoud, M., Elmasry, M.

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Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling von Elhossini, Ahmed, Areibi, Shawki, Dony, Robert

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Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique von Anis, Mohab, Mahmoud, Mohamed, Elmasry, Mohamed, Areibi, Shawki

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A Power-Efficient Multipin ILP-Based Routing Technique von Youssef, A., Zhen Yang, Anis, M., Areibi, S., Vannelli, A., Elmasry, M.

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A hardware/software co-design architecture for packet classification von Ahmed, O, Chattha, K, Areibi, S

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An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers von Armstrong, E, Grewal, G, Areibi, S, Darlington, G

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An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C von Walton, M., Ahmed, O., Grewal, G., Areibi, Shawki

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