Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation von Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

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Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias von Araga, Yuuki, Kikuchi, Katsuya, Aoyagi, Masahiro

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Validation of TSV thermo-mechanical simulation by stress measurement von Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

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Fabrication and stress analysis of annular-trench-isolated TSV von Feng, Wei, Bui, Tung Thanh, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

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Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer von Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

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Investigation of transient thermal dissipation in thinned LSI for advanced packaging von Araga, Yuuki, Shimamoto, Haruo, Melamed, Samson, Kikuchi, Katsuya, Aoyagi, Masahiro

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A novel method of hotspot temperature reduction for a 3D stacked CMOS IC chip device fabricated on an ultrathin substrate von Kato, Fumiki, Nakagawa, Hiroshi, Aoyagi, Masahiro

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Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer von Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

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Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits von Melamed, Samson, Imura, Fumito, Nakagawa, Hiroshi, Kikuchi, Katsuya, Hagimoto, Michiya, Matsumoto, Yukoh, Aoyagi, Masahiro

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Hardness Characteristics of Au Cone-Shaped Bumps Targeted for 3-D Packaging Applications von Lim, Ying Ying, Nakagawa, Hiroshi, Hashino, Masaru, Aoyagi, Masahiro, Kikuchi, Katsuya

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Fine Cone-shaped Bumps for Three-dimensional LSI Package—An Optimization of Thermocompression Bonding Process von Nemoto, Shunsuke, Lim, Ying Ying, Nakagawa, Hiroshi, Kikuchi, Katsuya, Aoyagi, Masahiro

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Novel through silicon via exposure process comprising Si/Cu grinding, electroless Ni-B plating, and wet etching of Si von Watanabe, Naoya, Aoyagi, Masahiro, Katagawa, Daisuke, Bandoh, Tsubasa, Yamamoto, Eiichi

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Investigation of metal contamination induced by a through silicon via reveal process using direct Si/Cu grinding and residual metal removal von Watanabe, Naoya, Aoyagi, Masahiro, Katagawa, Daisuke, Bandoh, Tsubasa, Mitsui, Takahiko, Yamamoto, Eiichi

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Damage Evaluation of Wet-Chemical Si-Wafer Thinning/Backside Via Exposure Process von Watanabe, Naoya, Miyazaki, Takumi, Yoshikawa, Kazuhiro, Aoyagi, Masahiro

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Fabrication of a membrane probe card using transparent film for three-dimensional integrated circuit testing von Watanabe, Naoya, Suzuki, Motohiro, Kawano, Kenji, Eto, Michiyuki, Aoyagi, Masahiro

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A method enabling height-control of chips for edge-emitting laser stacking von Tung, Bui Thanh, Ma, Laina, Amano, Takeru, Kikuchi, Katsuya, Mori, Masahiko, Aoyagi, Masahiro

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Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics--Optics Heterogeneous Integration von Tung, Bui Thanh, Suzuki, Motohiro, Kato, Fumiki, Nemoto, Shunsuke, Watanabe, Naoki, Aoyagi, Masahiro

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Anisotropic Deposition of Localized Electroless Nickel for Preferential Bridge Connection von Yokoshima, Tokihiko, Yamaji, Yasuhiro, Kikuchi, Katsuya, Nakagawa, Hiroshi, Aoyagi, Masahiro

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Impact of joint materials on the reliability of double-side packaged SiC power devices during high temperature aging von Lang, Fengqun, Nakagawa, Hiroshi, Aoyagi, Masahiro, Ohashi, Hiromichi, Yamaguchi, Hiroshi

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Message from the Editor von Aoyagi, Masahiro

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