Design of Approximate Restoring Dividers for Error Resilient Applications von Gowtham, P, Sasipriya, P, Anita Angeline, A

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Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications von Gundavarapu, Vishal, Gowtham, P., Anita Angeline, A., Sasipriya, P.

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High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits von Anita Angeline, A., Kanchana Bhaaskaran, V. S.

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Domino Logic Keeper Circuit Design Techniques: A Review von Angeline, A. Anita, Bhaaskaran, V. S. Kanchana

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Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit von Bhalerao, Abhishek L, Mane, Aishwarya, Pensenwar, Kartik, Bhuvana, B P, Anita Angeline, A, Kanchana Bhaaskaran, V S

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High speed wide fan-in designs using clock controlled dual keeper domino logic circuits von Angeline, A. Anita, Bhaaskaran, V.S. Kanchana

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Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit von Angeline, A. Anita, Kanchana Bhaaskaran, V.S

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Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic von Kushal Kumar, S V, Anita Angeline, A.

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Low Power Memory System Design Using Power Gated SRAM Cell von Pal, Srijani, Salimath, Divya S, Chandran, Banusha, Anita Angeline, A, Kanchana Bhaaskaran, V S

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Schmitt Trigger Designs Using Domino Logic Style von Singh, Nikhil, Shekhar, Siddharth, Angeline, Anita, Bhaaskaran V. S, Kanchana

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High Performance Wallace Tree Multiplier Using Majority Gate Based Adders von Mummudi Murasu, M, Sujith, Sanjana, Anita Angeline, A, Sasi Priya, P., Kanchana Bhaaskaran, V S

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Design of a 16 Bit RISC Processor von Vishnuvardhan Rao, K., Anita Angeline, A., Kanchana Bhaaskaran, V. S.

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Dynamic Logic ALU Design with Reduced Switching Power von Khaladkar, Ramdas Bhanudas, Anita Angeline, A., Kanchana Bhaaskaran, V. S.

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FFT and Linear Convolution Implementation with Bit Slicing Multiplier: A Novel Approach von N, Aravind Kumar, S, Hari Krishna, A, Anita Angeline

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Response of the Intertropical Convergence Zone to Climate Change: Location, Width, and Strength von Byrne, Michael P., Pendergrass, Angeline G., Rapp, Anita D., Wodzicki, Kyle R.

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FFT and Linear Convolution Implementation with Bit Slicing Multiplier: A Novel Approach von Aravind, Kumar N, Hari, Krishna S, Anita, Angeline A

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Response of the Intertropical Convergence Zone to Climate Change: Location, Width, and Strength von Byrne, Michael P., Pendergrass, Angeline G., Rapp, Anita D., Wodzicki, Kyle R.

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Design and Implementation of Multi-bit Self-checking Carry Select Adder von Kavitkar, Shivkumar, Anita Angeline, A.

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High Performance Domino Logic Circuit Design by Contention Reduction von Anita Angeline, A., Kanchana Bhaaskaran, V. S.

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Angéline, l'enfant marquée : roman / Anita Pereire von Pereire, Anita. Author of the text, Pereire, Anita. Auteur du texte

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