Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm von Taneja, Sachin, Alvarez, Anastacia B., Alioto, Massimo

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Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology von Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Alvarez, Anastacia B.

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Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL von Reas, Rosario M, Alvarez, Anastacia B, Reyes, Joy Alinda P

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Implementation of the Phase II Compiler for the ARM7TDMI-S Dual-Core Microprocessor von Sebastian, Sherry Joy Alvionne V, Tang, Alvin Joseph J, Alvarez, Anastacia B, Madamba, Joy Alinda R

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Comparative study of low-leakage SRAM structures using 90nm CMOS technology von Domingo, M E B, Ostia, F I, Reas, R M, Alvarez, A B, Alarcon, L P

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Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology von Zhao, Wenfeng, Ha, Yajun, Hoo, Chin Hau, Alvarez, Anastacia B.

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Static Noise Margin of 6T SRAM Cell in 90-nm CMOS von Arandilla, C D C, Alvarez, A B, Roque, C R K

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A test port for interfacing and debugging ARM9 processors implemented in FPGA von Fabay, K. B. F., Jardin, J. C. F., Jocson, K. J. C., Pelayo, B. R. D., Alvarez, A. B., Madamba, J. A. R., Alarcon, L. P.

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High-level implementation of the 5-stage pipelined ARM9TDM core von Arandilla, C C, Constantino, J B A, Glova, A O M, Ballesil-Alvarez, A P, Reyes, J A P

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