On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions von Haurylau, M., Guoqing Chen, Hui Chen, Jidong Zhang, Nelson, N.A., Albonesi, D.H., Friedman, E.G., Fauchet, P.M.

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Dynamically tuning processor resources with adaptive processing von Albonesi, D. H., Balasubramonian, R., Dropsbo, S. G., Dwarkadas, S., Friedman, E. G., Huang, M. C., Kursun, V., Magklis, G., Scott, M. L., Semeraro, G., Bose, P., Buyuktosunoglu, A., Cook, P. W., Schuster, S. E.

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Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor von Magklis, G., Semeraro, G., Albonesi, D.H., Dropsho, S.G., Dwarkadas, S., Scott, M.L.

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Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling von Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Scott, M.L.

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Front-end policies for improved issue efficiency in SMT processors von El-Moursy, A., Albonesi, D.H.

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A dynamically tunable memory hierarchy von Balasubramonian, R., Albonesi, D.H., Buyuktosunoglu, A., Dwarkadas, S.

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Selective cache ways: on-demand cache resource allocation von Albonesi, D.H.

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Dynamically allocating processor resources between nearby and distant ILP von Balasubramonian, Rajeev, Dwarkadas, Sandhya, Albonesi, David H.

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Power-efficient error tolerance in chip multiprocessors von Rashid, M.W., Tan, E.J., Huang, M.C., Albonesi, D.H.

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ReMAP: A Reconfigurable Heterogeneous Multicore Architecture von Watkins, M A, Albonesi, D H

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ReMAP: A Reconfigurable Architecture for Chip Multiprocessors von Watkins, M A, Albonesi, D H

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Electrical and optical on-chip interconnects in scaled microprocessors von Guoqing Chen, Hui Chen, Haurylau, M., Nelson, N., Albonesi, D., Fauchet, P.M., Friedman, E.G.

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Integrating adaptive on-chip storage structures for reduced dynamic power von Dropsho, S., Buyuktosunoglu, A., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Semeraro, G., Magklis, G., Scottt, M.L.

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Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures von Balasubramonian, R., Albones, D., Buyuktosunoglu, A., Dwarkadas, S.

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Dynamic data dependence tracking and its application to branch prediction von Lei Chen, Dropsho, S., Albonesi, D.H.

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On-Chip Optical Technology in Future Bus-Based Multicore Designs von Kirman, Nevin, Kirman, Meyrem, Dokania, Rajeev K., Martinez, Jose F., Apsel, Alyssa B., Watkins, Matthew A., Albonesi, David H.

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Early-Stage Definition of LPX: A Low Power Issue-Execute Processor von Bose, P., Brooks, D., Buyuktosunoglu, A., Cook, P., Das, K., Emma, P., Gschwind, M., Jacobson, H., Karkhanis, T., Kudva, P., Schuster, S., Smith, J., Srinivasan, V., Zyuban, V., Albonesi, D., Dwarkadas, S.

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A mean value analysis multiprocessor model incorporating superscalar processors and latency tolerating techniques von ALBONESI, D. H, KOREN, I

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Dynamic frequency and voltage control for a multiple clock domain microarchitecture von Semeraro, G., Albonesi, D.H., Dropsho, S.G., Magklis, G., Dwarkadas, S., Scott, M.L.

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Dynamically managing the communication-parallelism trade-off in future clustered processors von Balasubramonian, Rajeev, Dwarkadas, Sandhya, Albonesi, David H

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