Indexed BDDs: algorithmic advances in techniques to represent and verify Boolean functions von Jain, J., Bitner, J., Abadir, M.S., Abraham, J.A., Fussell, D.S.

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An experiment of burn-in time reduction based on parametric test analysis von Sumikawa, N., Wang, Li-C., Abadir, M. S.

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Formal Verification Successes at Motorola von Abadir, Magdy S., Albin, Kenneth L., Havlicek, John, Krishnamurthy, Narayanan, Martin, Andrew K.

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Functional test generation using binary decision diagrams von Abadir, M.S., Reghbati, H.K.

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Establishing latch correspondence for embedded circuits of PowerPC microprocessors von Anand, H., Bhadra, J., Sen, A., Abadir, M.S., Davis, K.G.

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Statistical outlier screening for latent defects von Tikkanen, J., Sumikawa, N., Wang, L., Winemberg, L., Abadir, M. S.

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Forward prediction based on wafer sort data - A case study von Sumikawa, N., Drmanac, D. G., Wang, Li-C, Winemberg, L., Abadir, M. S.

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Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits von Drmanac, D, Sumikawa, N, Winemberg, L, Wang, Li-C, Abadir, M S

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Design rewiring using ATPG von Veneris, A., Abadir, M.S.

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Validating Power Architectureac Technology-Based MPSoCs Through Executable Specifications von Bhadra, J, Trofimova, E, Abadir, MS

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A Statistical Diagnosis Approach for Analyzing DesignaSilicon Timing Mismatch von Callegari, N, Bastani, P, Wang, L-C, Abadir, MS

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Post-verification debugging of hierarchical designs von Ali, M. F., Safarpour, S., Veneris, A., Abadir, M. S., Drechsler, R.

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Enhanced equivalence checking: toward a solidarity of functional verification and manufacturing test generation von Jayanta Bhadra, Krishnamurthy, N., Abadir, M.S.

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Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams von ABADIR, M. S, REGHBATI, H. K

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Very low cost testers: Opportunities and challenges von Bedsole, J., Raina, R., Crouch, A., Abadir, M.S.

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Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG von Veneris, Andreas, Chang, Robert, Abadir, Magdy S, Seyedi, Sep

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Validating PowerPC microprocessor custom memories von Krishnamurthy, N., Martin, A.K., Abadir, M.S., Abraham, J.A.

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Functional specification and testing of logic circuits von Abadir, M.S., Reghbati, H.K.

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On correlating structural tests with functional tests for speed binning of high performance design von Zeng, J., Abadir, M.S., Vandling, G., Wang, L.-C., Karako, S., Abraham, J.A.

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Enhanced symbolic simulation for efficient verification of embedded array systems von Tao Feng, Wang, L.-C., Kwang-Ting Cheng, Pandey, M., Abadir, M.S.

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