The Effect of Gate Bias on Hot Electron Trapping von Matsumoto, Heihachi, Sawada, Kokichi, Asai, Sotoju, Hirayama, Makoto, Nagasawa, Koichi

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An 80-MHz 8-bit CMOS D/A converter von Miki, T., Nakamura, Y., Nakaya, M., Asai, S., Akasaka, Y., Horiba, Y.

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Effect of Long Term Stress on Hot Electron Trapping von Matsumoto, Heihachi, Sawada, Kokichi, Asai, Sotoju, Hirayama, Makoto, Nagasawa, Koichi

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An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI von Watabe, K., Akiyama, H., Terashima, T., Okada, M., Nobuto, S., Yamawaki, M., Asai, S.

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Quantitative Evaluation Technique of Narrow Width Effects on DD (Deep Depletion) MOSFETs and BCCDs von Yamamoto, Hidekazu, Kawashima, Hiroshi, Asai, Sotoju, Tsubouchi, Natsuro

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Expression of worst case using multivariate analysis in MOSFET model parameters von Yasuda, T., Kawashima, H., Hori, S., Tanizawa, M., Yamawaki, M., Asai, S.

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An 8-bit high-speed CMOS A/D converter von Kumamoto, T., Nakaya, M., Honda, H., Asai, S., Akasaka, Y., Horiba, Y.

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Complementary field-effect transistor von TOKUDA,TAKESHI, ASAI,SOTOJU

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Effect of long-term stress on IGFET degradations due to hot electron trapping von Matsumoto, H., Sawada, K., Asai, S., Hirayama, M., Nagasawa, K.

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Time Dependent Dielectric Breakdown of Thin SiO 2 Films von Hirayama, Makoto, Asai, Sotoju, Matsumoto, Heihachi, Sawada, Kokichi, Nagasawa, Koichi

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A configurable ROM circuit for use in gate arrays von Ueda, M., Sakashita, K., Arakawa, T., Okazaki, K., Asai, S., Kuramitsu, Y.

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Solid state image sensing device and a method of manufacturing the same von KIMATA, MASAFUMI, ASAI, SOTOJU, YAMAWAKI, MASAO

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A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure von Sakashita, K., Ueda, M., Arakawa, T., Asai, S., Fujimura, T., Ohkura, I.

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Solid state image sensing device and a method of manufacturing the same von ASAI, SOTOJU, KIMATA, MASAFUMI, YAMAWAKI, MASAO

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A digital processor for decoding composite TV signals using adaptive filtering von Murakami, K., Nakagawa, S., Yoshimoto, M., Asai, S., Akasaka, Y., Nakajima, Y., Horiba, Y.

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A 10K-gate CMOS gate array based on a gate isolation structure von Sakashita, K., Ueda, M., Arakawa, T., Asai, S., Fujimura, T., Ohkura, I.

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A Hierarchical Standard Cell Approach for Custom VLSI Design von Tokuda, T., Korematsu, J., Tomisawa, O., Asai, S., Ohkura, I., Enomoto, T.

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Solid-state image sensor von YAMAMOTO, HIDEKAZU, YUTANI, NAOKI, ASAI, SOTOJU, HIROSE, SATOSHI, HINE, SHIRO, UENO, MASASHI

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DE3414772 von ASAI, SOTOJU, TOYONO, OSAKA, JP, TOKUDA, TAKESHI, ITAMI, HYOGO, JP

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FESTKOERPERBILDSENSOR von HINE,SHIRO, HIROSE,SATOSHI, YAMAMOTO,HIDEKAZU, UENO,MASASHI, YUTANI,NAOKI, ASAI,SOTOJU

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