Suchergebnisse - AKELLA SASTRY

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Application of Web Services in SCADA Systems von Kelapure, Shekhar M, Akella, S.S.K. Sastry, Gopala Rao, J

Veröffentlicht in International Journal of Emerging Electric Power Systems

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Packet identification (ID) assignment for routing network von Singh, Abnikant, Surendran, Rishi, Sastry, Akella

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Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddharth, Sastry, Akella, Hunsigida, Vidhumouli

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HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES von GUPTA, Shail, Aditya, HUNSIGIDA, Vidhumouli, HWANG, L., James, RELE, Siddharth, SASTRY, Akella, KATHAIL, Vinod K

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HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddharth, Sastry, Akella, Hunsigida, Vidhumouli

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Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddharth, Sastry, Akella, Hunsigida, Vidhumouli

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DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM von JAMES-ROXBY, Philip B, SASTRY, Akella, GUPTA, Shail Aditya, BAYLISS, Samuel R, KATHAIL, Vinod K, WITTIG, Ralph D

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DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM von KATHAIL, Vinod, JAMES-ROXBY, Philip B, SASTRY, Akella, GUPTA, Shail Aditya, BAYLISS, Samuel R, WITTIG, Ralph D

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Dataflow graph programming environment for a heterogenous processing system von Kathail, Vinod K, Bayliss, Samuel R, Gupta, Shail Aditya, James-Roxby, Philip B, Wittig, Ralph D, Sastry, Akella

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A DEMAND-DRIVEN ALGORITHM TO REDUCE SIGN-EXTENSION INSTRUCTIONS INCLUDED IN LOOPS OF A 64-BIT COMPUTER PROGRAM von LIN, YUAN, SASTRY, AKELLA

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DEMAND-DRIVEN ALGORITHM TO REDUCE SIGN-EXTENSION INSTRUCTIONS INCLUDED IN LOOPS OF A 64-BIT COMPUTER PROGRAM von LIN YUAN, SASTRY AKELLA

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HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddarth, Sastry, Akella, Hunsigida, Vidhumouli

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COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE von GUPTA, Shail, Aditya, AGARWAL, Ajit, K, SURENDRAN, Rishi, WITTIG, Ralph, D, SASTRY, Akella, SIVARAMAN, Mukund, KATHAIL, Vinod, K, BAYLISS, Samuel, R, JAMES-ROXBY, Philip, B

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DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM von Kathail, Vinod K, Bayliss, Samuel R, Gupta, Shail Aditya, James-Roxby, Philip B, Wittig, Ralph D, Sastry, Akella

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Compilation flow for a heterogeneous multi-core architecture von Kathail, Vinod K, Agarwal, Ajit K, Bayliss, Samuel R, Sivaraman, Mukund, Gupta, Shail Aditya, James-Roxby, Philip B, Surendran, Rishi, Wittig, Ralph D, Sastry, Akella

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COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE von Kathail, Vinod K, Agarwal, Ajit K, Bayliss, Samuel R, Sivaraman, Mukund, Gupta, Shail Aditya, James-Roxby, Philip B, Surendran, Rishi, Wittig, Ralph D, Sastry, Akella

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A demand-driven algorithm to reduce sign-extension instructions included in loops of a 64-bit computer program von LIN, YUAN, SASTRY, AKELLA

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AN INTERMEDIATE REPRESENTATION FOR MULTIPLE EXCEPTION HANDLING MODELS von SASTRY, AKELLA, V., S, GROVER, VINOD, K

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이종 및 프로그램 가능 디바이스를 위한 고수준 합성을 갖는 하드웨어-소프트웨어 설계 흐름 von HWANG L. JAMES, KATHAIL VINOD K, GUPTA SHAIL ADITYA, HUNSIGIDA VIDHUMOULI, RELE SIDDHARTH, SASTRY AKELLA

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Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices von HWANG L J, KATHAIL VINOD K, HUNSIGIDA VIDHUMOULI, GUPTA SHAIL, SASTRY AKELLA, RELE SIDDARTH

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Application of Web Services in SCADA Systems von Kelapure, Shekhar M, Akella, S.S.K. Sastry, Gopala Rao, J

Packet identification (ID) assignment for routing network von Singh, Abnikant, Surendran, Rishi, Sastry, Akella

Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddharth, Sastry, Akella, Hunsigida, Vidhumouli

HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES von GUPTA, Shail, Aditya, HUNSIGIDA, Vidhumouli, HWANG, L., James, RELE, Siddharth, SASTRY, Akella, KATHAIL, Vinod K

HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddharth, Sastry, Akella, Hunsigida, Vidhumouli

Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddharth, Sastry, Akella, Hunsigida, Vidhumouli

DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM von JAMES-ROXBY, Philip B, SASTRY, Akella, GUPTA, Shail Aditya, BAYLISS, Samuel R, KATHAIL, Vinod K, WITTIG, Ralph D

DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM von KATHAIL, Vinod, JAMES-ROXBY, Philip B, SASTRY, Akella, GUPTA, Shail Aditya, BAYLISS, Samuel R, WITTIG, Ralph D

Dataflow graph programming environment for a heterogenous processing system von Kathail, Vinod K, Bayliss, Samuel R, Gupta, Shail Aditya, James-Roxby, Philip B, Wittig, Ralph D, Sastry, Akella

A DEMAND-DRIVEN ALGORITHM TO REDUCE SIGN-EXTENSION INSTRUCTIONS INCLUDED IN LOOPS OF A 64-BIT COMPUTER PROGRAM von LIN, YUAN, SASTRY, AKELLA

DEMAND-DRIVEN ALGORITHM TO REDUCE SIGN-EXTENSION INSTRUCTIONS INCLUDED IN LOOPS OF A 64-BIT COMPUTER PROGRAM von LIN YUAN, SASTRY AKELLA

HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES von Kathail, Vinod K, Hwang, L. James, Gupta, Shail Aditya, Rele, Siddarth, Sastry, Akella, Hunsigida, Vidhumouli

COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE von GUPTA, Shail, Aditya, AGARWAL, Ajit, K, SURENDRAN, Rishi, WITTIG, Ralph, D, SASTRY, Akella, SIVARAMAN, Mukund, KATHAIL, Vinod, K, BAYLISS, Samuel, R, JAMES-ROXBY, Philip, B

DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM von Kathail, Vinod K, Bayliss, Samuel R, Gupta, Shail Aditya, James-Roxby, Philip B, Wittig, Ralph D, Sastry, Akella

Compilation flow for a heterogeneous multi-core architecture von Kathail, Vinod K, Agarwal, Ajit K, Bayliss, Samuel R, Sivaraman, Mukund, Gupta, Shail Aditya, James-Roxby, Philip B, Surendran, Rishi, Wittig, Ralph D, Sastry, Akella

COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE von Kathail, Vinod K, Agarwal, Ajit K, Bayliss, Samuel R, Sivaraman, Mukund, Gupta, Shail Aditya, James-Roxby, Philip B, Surendran, Rishi, Wittig, Ralph D, Sastry, Akella

A demand-driven algorithm to reduce sign-extension instructions included in loops of a 64-bit computer program von LIN, YUAN, SASTRY, AKELLA

AN INTERMEDIATE REPRESENTATION FOR MULTIPLE EXCEPTION HANDLING MODELS von SASTRY, AKELLA, V., S, GROVER, VINOD, K

이종 및 프로그램 가능 디바이스를 위한 고수준 합성을 갖는 하드웨어-소프트웨어 설계 흐름 von HWANG L. JAMES, KATHAIL VINOD K, GUPTA SHAIL ADITYA, HUNSIGIDA VIDHUMOULI, RELE SIDDHARTH, SASTRY AKELLA

Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices von HWANG L J, KATHAIL VINOD K, HUNSIGIDA VIDHUMOULI, GUPTA SHAIL, SASTRY AKELLA, RELE SIDDARTH

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