A 58-nm 2-Gb MLC "B4-Flash" Memory with Flexible Multisector Architecture von Ogura, Taku, Kasa, Yasushi, Kurosaki, Kazuhide, Tomoeda, Mitsuhiro, Otoi, Hisakazu, Shimizu, Satoshi, Katsumata, Masafumi, Ajika, Natsuo, Kobayashi, Kazuo

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Optimization of nitridation and reoxidation conditions for an EEPROM tunneling dielectric von ARIMA, H, AJIKA, N, OHI, M, SAKAMOTO, O, MATSUKAWA, T, TSUBOUCHI, N

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Atomic structure images formed by plasma-loss electrons von AJIKA, N, HASHIMOTO, H, YAMAGUCHI, K, ENDOH, H

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Bipolar transistor selected P-channel flash memory cell technology von Ohnakado, T., Ajika, N., Satoh, S.

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Influence of holes on neutral trap generation von Sakakibara, K., Ajika, N., Miyoshi, H.

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A 60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot-Electron Injection (B4-Flash) von Shukuri, S., Ajika, N., Mihara, M., Kobayashi, K., Endoh, T., Nakashima, M.

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Device characteristics of 0.35 μm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming von Ohnakado, T., Onoda, H., Sakamoto, O., Hayashi, K., Nishioka, N., Takada, H., Sugahara, K., Ajika, N., Satoh, S.

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On a universal parameter of intrinsic oxide breakdown based on analysis of trap-generation characteristics von Sakakibara, K., Ajika, N., Miyoshi, H.

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A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications von Nozoe, A., Kotani, H., Tsujikawa, T., Yoshida, K., Furusawa, K., Kato, M., Nishimoto, T., Kume, H., Kurata, H., Miyamoto, N., Kubono, S., Kanamitsu, M., Koda, K., Nakayama, T., Kouro, Y., Hosogane, A., Ajika, N., Koyashi, K.

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Detailed observation of small leak current in flash memories with thin tunnel oxides von Manabe, Y., Okuyama, K., Kubota, K., Nozoe, A., Karashima, T., Ujiie, K., Kanno, H., Nakashima, M., Ajika, N.

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Non-volatile semiconductor memory device comprising capacitive coupling program inhibit circuitry von Ogura, Taku, Ajika, Natsuo

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Non-volatile semiconductor memory device comprising capacitive coupling program inhibit circuitry von OGURA TAKU, AJIKA NATSUO

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Identification of stress-induced leakage current components and the corresponding trap models in SiO sub(2) films von Sakakibara, Kiyohiko, Ajika, Natsuo, Hatanaka, Masahiro, Miyoshi, Hirokazu, Yasuoka, Akihiko

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Identification of stress-induced leakage current components and the corresponding trap models in SiO sub(2) films von Sakakibara, Kiyohiko, Ajika, Natsuo, Hatanaka, Masahiro, Miyoshi, Hirokazu, Yasuoka, Akihiko

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Quantitative analysis of time-decay reproducible stress-induced leakage current in SiO sub(2) films von Sakakibara, Kiyohiko, Ajika, Natsuo, Eikyu, Katsumi, Ishikawa, Kiyoshi, Miyoshi, Hirokazu

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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME von OGURA TAKU, AJIKA NATSUO

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Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor von OGURA TAKU, AJIKA NATSUO, MIHARA MASAAKI

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METHOD OF ERASING NONVOLATILE SEMICONDUCTOR MEMORY von AJIKA NATSUO

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NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE von NATSUO AJIKA

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NON-VOLATILE MEMORY TRANSISTOR AND ITS MANUFACTURING METHOD von AJIKA NATSUO, YADORI SHOJI

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