A 553K-transistor LISP processor chip von BOSSHART, P. W, HEWES, C. R, MAHANT-SHETTI, S. S, MATZKE, D. J, RUPAREL, K. N, SEXTON, J. F, CHING-HAO SHAW, SRIDHAR, T, STARK, D, AH LYAN LEE, ALES, M. D, MI-CHANG CHANG, KWOK KIT CHAU, FASHAM, K, HOAC, C. C, HOUSTON, T. W, VIBHU KALYAN, LUSKY, S. L

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A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels von PAYNE, Robert, LANDMAN, Paul, YIQUN XIE, PARTHASARATHY, Bharadwaj, BROUSE, Keith, MOHAMMED, Wahed, HERAGU, Keerthi, GUPTA, Vikas, DYSON, Lisa, LEE, Wai, BHAKTA, Bhavesh, RAMASWAMY, Sridhar, SONG WU, POWERS, John D, ULVI ERDOGAN, M, YEE, Ah-Lyan, GU, Richard, LIN WU

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A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications von Payne, R., Bhakta, B., Ramaswamy, S., Song Wu, Powers, J., Landman, P., Erdogan, U., Ah-Lyan Yee, Gu, R., Lin Wu, Yiqun Xie, Parthasarathy, B., Brouse, K., Mohammed, W., Heragu, K., Gupta, V., Dyson, L., Wai Lee

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A 6.25GHz 1V LC-PLL in 0.13/spl mu/m CMOS von Richard Gu, Ah-Lyan Yee, Yiqun Xie, Wai Lee

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A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications von Landman, P., Brouse, K., Gupta, V., Song Wu, Payne, R., Erdogan, U., Gu, R., Ah-Lyan Yee, Parthasarathy, B., Ramaswamy, S., Bhakta, B., Mohammed, W., Powers, J., Yiqun Xie, Lin Wu, Dyson, L., Heragu, K., Wai Lee

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A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology von Landman, P., Ah-Lyan Yee, Gu, R., Parthasarathy, B., Gupta, V., Ramaswamy, S., Dyson, L., Bosshart, P., Reynolds, J., Frannhagen, M., Fremrot, P., Johansson, S., Lewis, K., Wai Lee

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A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology von Landman, P., Ah-Lyan Yee, Gu, R., Parthasarathy, B., Gupta, V., Ramaswamy, S., Dyson, L., Bosshart, P., Reynolds, J., Frannhagen, M., Fremrot, P., Johansson, S., Lewis, K., Lee, W.

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