Design Approach for Fault Tolerance in FPGA Architecture von Meshram, Shweta S, Belorkar, Ujwala A

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Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology von A. Belorkar, Ujwala, Ladhake, S.A

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VLSI Implementation of Back Propagated Neural Network for Signal Processing von Belorkar, Ujwala A, Bhande, Ashish E

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High Speed Convolution and Deconvolution Algorithm based on Ancient Indian Vedic Mathematics von Belorkar, Ujwala A, Bhande, Ashish E

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Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology von A. Belorkar, Ujwala, S.A, Ladhake

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Redundancy for Fault Tolerance Algorithm in FPGA Architecture for Reliability with a BIST Approach von Meshram, Shweta S, Belorkar, Ujwala A

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RF mixer design for 10.5 GHz, using 0.18µm CMOS technology von Vyas, Archana O, Belorkar, Ujwala A

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2.45 GHz Gilbert mixer using 45 nm CMOS technology von Belorkar, U. A., Ladhake, S. A., Kale, S. N.

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Application of 45 nm VLSI Technology to design layout of static RAM memory von Belorkar, Ujwala Ajabrao, Ladhake, Sidharth A

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